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51. 发明申请

US20120292597A1 Self-Aligned Contacts in Carbon Devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US20120292597A1
公开(公告)日：2012-11-22
申请号：US13562827
申请日：2012-07-31
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/775
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.
摘要翻译：半导体器件包括设置在基底上的碳层，设置在碳层的一部分上的栅极叠层，由碳层和衬底限定的第一腔，由碳层和衬底限定的第二腔，源区域，包括设置在第一腔中的第一导电触点，漏区，包括设置在第二腔中的第二导电触点。

52. 发明申请

US20120286366A1 Field Effect Transistor Device and Fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US20120286366A1
公开(公告)日：2012-11-15
申请号：US13554294
申请日：2012-07-20
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L27/092
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
摘要翻译：在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

53. 发明申请

US20120280279A1 Field Effect Transistor Device with Shaped Conduction Channel 有权
标题翻译：具有形状导通通道的场效应晶体管器件
公开(公告)号：US20120280279A1
公开(公告)日：2012-11-08
申请号：US13551164
申请日：2012-07-17
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
摘要翻译：场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料，填充空腔的金属栅极材料，源极区域和漏极区域。

54. 发明申请

US20120199941A1 SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) 有权
标题翻译：应力衬里上的硅半导体器件（SOL）
公开(公告)号：US20120199941A1
公开(公告)日：2012-08-09
申请号：US13365764
申请日：2012-02-03
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

55. 发明授权

US08105893B2 Diffusion sidewall for a semiconductor structure 有权
标题翻译：用于半导体结构的扩散侧壁
公开(公告)号：US08105893B2
公开(公告)日：2012-01-31
申请号：US12621216
申请日：2009-11-18
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L21/8238
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
摘要翻译：在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

56. 发明申请

US20120007054A1 Self-Aligned Contacts in Carbon Devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US20120007054A1
公开(公告)日：2012-01-12
申请号：US12832224
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/76 , H01L29/78 , H01L27/12 , H01L29/24 , H01L21/86 , H01L21/04
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
摘要翻译：一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及在所述至少一个空腔中形成导电接触。

57. 发明申请

US20110248362A1 SELF-ALIGNED CONTACTS 有权
标题翻译：自对准联系人
公开(公告)号：US20110248362A1
公开(公告)日：2011-10-13
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E.A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E.A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.
摘要翻译：提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

58. 发明申请

US20110215300A1 GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE 有权
标题翻译：基于GRAPHENE的三维集成电路设备
公开(公告)号：US20110215300A1
公开(公告)日：2011-09-08
申请号：US12719058
申请日：2010-03-08
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L27/088 , H01L21/8256
CPC分类号： H01L27/0688 , H01L29/1606 , Y10S977/755
摘要： A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.
摘要翻译：三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

59. 发明申请

US20110163380A1 Body-Tied Asymmetric N-Type Field Effect Transistor 有权
标题翻译：体态不对称N型场效应晶体管
公开(公告)号：US20110163380A1
公开(公告)日：2011-07-07
申请号：US12683634
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66659 , H01L29/66772 , H01L29/78615
摘要： In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称N型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称N型场效应晶体管可用作对称N型场效应晶体管。

60. 发明授权

US09041057B2 Field effect transistor device with shaped conduction channel 有权
标题翻译：具有形状导通通道的场效应晶体管器件
公开(公告)号：US09041057B2
公开(公告)日：2015-05-26
申请号：US13551164
申请日：2012-07-17
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L29/10 , H01L29/165 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
摘要翻译：场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料，填充空腔的金属栅极材料，源极区域和漏极区域。

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