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51. 发明授权

US06913987B2 Method for fabricating self-aligned contact connections on buried bit lines 失效
标题翻译：用于在掩埋位线上制造自对准接触连接的方法
公开(公告)号：US06913987B2
公开(公告)日：2005-07-05
申请号：US10728388
申请日：2003-12-05
申请人： Juerg Haufe , Josef Willer
发明人： Juerg Haufe , Josef Willer
IPC分类号： H01L21/283 , H01L21/3205 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/76897 , H01L27/115
摘要： Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word lines. The spacers are subsequently covered together with the word lines with a nitride layer. Borophosporosilicate glass is introduced between those portions of the nitride layer which respectively belong to a word line and is removed selectively with respect to the nitride using a mask. Contact hole fillings for the electrical connection of the buried bit lines are introduced into the contact holes thus formed.
摘要翻译：半导体元件的字线被提供有电介质材料的封装，氧化物隔离物在字线的侧壁旁边延伸。间隔物随后用氮化物层与字线一起被覆盖。硼氮硅玻璃被引入到分别属于字线的氮化物层的这些部分之间并且使用掩模相对于氮化物被选择性地去除。将掩埋位线的电连接的接触孔填充物引入由此形成的接触孔中。

52. 发明申请

US20050067659A1 Memory cell with nanocrystals or nanodots 有权
标题翻译：具有纳米晶体或纳米点的记忆体
公开(公告)号：US20050067659A1
公开(公告)日：2005-03-31
申请号：US10916013
申请日：2004-08-11
申请人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
发明人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).
摘要翻译：存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。栅电极（5）通过导电间隔物（7）在侧面加宽。

53. 发明授权

US06844584B2 Memory cell, memory cell configuration and fabrication method 有权
标题翻译：存储单元，存储单元配置和制造方法
公开(公告)号：US06844584B2
公开(公告)日：2005-01-18
申请号：US09927573
申请日：2001-08-09
申请人： Herbert Palm , Josef Willer , Achim Gratz , Jakob Kriz , Mayk Roehrich
发明人： Herbert Palm , Josef Willer , Achim Gratz , Jakob Kriz , Mayk Roehrich
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.
摘要翻译：每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。栅电极通过介电材料与半导体材料分离。至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氧化物 - 氧化物层序列。层序列是为了在源极和漏极处俘获电荷载体而提供的。

54. 发明授权

US06686242B2 Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array 有权
标题翻译：用于制造用于存储单元阵列的金属位线的方法，用于制造存储单元阵列的方法和存储单元阵列
公开(公告)号：US06686242B2
公开(公告)日：2004-02-03
申请号：US09917867
申请日：2001-07-26
申请人： Josef Willer , Ronald Kakoschke
发明人： Josef Willer , Ronald Kakoschke
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in said gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of said bit line recesses, whereupon a source/drain implantation is executed in the area of said bit line recesses, after a complete or partial removal of the sequence of storage medium layers. Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallizations for producing metallic bit lines are produced on the exposed substrate, said metallizations being insulated from the gate region layer by the insulating spacer layers.
摘要翻译：一种用于产生存储单元阵列的位线的方法包括作为第一步骤的步骤，提供包括在其表面上注入晶体管阱的衬底的层结构，设置在所述衬底的表面上的一系列存储介质层，以及设置在所述存储介质层序列上的栅极区域层。在所述栅极区域层中产生向下延伸到存储介质层序列的位线凹槽。随后，在所述位线凹槽的侧表面上产生绝缘间隔层，于是在完成或部分去除存储介质层序列之后，在所述位线凹槽的区域中执行源极/漏极注入。接下来，如果在植入之前还没有完成，则衬底完全暴露在位线凹槽的区域中。随后，在暴露的基板上制造用于制造金属位线的金属化，所述金属化通过绝缘间隔层与栅极区域层绝缘。

55. 发明授权

US06661053B2 Memory cell with trench transistor 有权
标题翻译：具有沟槽晶体管的存储单元
公开(公告)号：US06661053B2
公开(公告)日：2003-12-09
申请号：US10022654
申请日：2001-12-18
申请人： Josef Willer , Frank Lau , Dezsö Takacs
发明人： Josef Willer , Frank Lau , Dezsö Takacs
IPC分类号： H01L2976
CPC分类号： H01L29/792 , H01L27/115 , H01L29/78
摘要： A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source zone in the semiconductor body is doped from the top surface. A drain zone in the semiconductor body is doped from the top surface. Junctions of the source and drain zones are beneath each. A gate electrode on the top surface of the semiconductor body is disposed between the source zone and the drain zone in the trench. A dielectric layer isolates the gate electrode from the semiconductor body and acts as a storage medium. Each of the junctions intersects a respective one of the walls at a respective depth from the bottom. A respective spacing across the trench is defined at each depth.
摘要翻译：存储单元包括具有以下结构的存储晶体管，其尺寸被设计为缩短编程和擦除时间。半导体本体包括顶表面和形成在其中的具有由弯曲底部连接的壁的沟槽。半导体本体中的源区从顶表面掺杂。半导体本体中的漏极区域从上表面掺杂。源极和漏极区的接合点在每个下方。半导体本体的顶表面上的栅电极设置在沟槽中的源区和漏区之间。电介质层将栅电极与半导体本体隔离并用作存储介质。每个连接点在与底部相应的深度处与相应的一个壁相交。在每个深度处限定跨沟槽的相应间隔。

56. 发明授权

US06576948B2 Integrated circuit configuration and method for manufacturing it 有权
标题翻译：集成电路配置及其制造方法
公开(公告)号：US06576948B2
公开(公告)日：2003-06-10
申请号：US09873231
申请日：2001-06-04
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/108
摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.
摘要翻译：集成电路包含平面第一晶体管和二极管。二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。二极管可以配置为隧道二极管。二极管层可以通过热氧化生产。制造二极管只需要一个掩模。电容器可以设置在二极管的上方。电容器的第一电容器电极连接到导电结构。

57. 发明授权

US06521935B2 Mos transistor and dram cell configuration 有权
标题翻译：莫斯晶体管和电池组配置
公开(公告)号：US06521935B2
公开(公告)日：2003-02-18
申请号：US10027524
申请日：2001-12-26
申请人： Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/66666 , H01L29/7841 , H01L29/78642
摘要： A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
摘要翻译： MOS晶体管包括上层堆叠的上源极/漏极区，沟道区和下源极/漏极区，并且形成衬底的突起。栅极电介质邻接突起的第一横向区域。栅电极邻接栅极电介质。导电结构在通道区域的区域中毗邻突起的第二横向区域。导电结构邻接栅电极。

58. 发明授权

US06194765B1 Integrated electrical circuit having at least one memory cell and method for fabricating it 有权
标题翻译：具有至少一个存储单元的集成电路及其制造方法
公开(公告)号：US06194765B1
公开(公告)日：2001-02-27
申请号：US09313433
申请日：1999-05-17
申请人： Hans Reisinger , Reinhard Stengl , Ulrike Grüning , Volker Lehmann , Hermann Wendt , Josef Willer , Martin Franosch , Herbert Schäfer
发明人： Hans Reisinger , Reinhard Stengl , Ulrike Grüning , Volker Lehmann , Hermann Wendt , Josef Willer , Martin Franosch , Herbert Schäfer
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.
摘要翻译：集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。存储单元包含彼此电连接的至少两个反相器。反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。本发明还涉及一种用于制造集成电路的方法。

59. 发明授权

US4889827A Method for the manufacture of a MESFET comprising self aligned gate 失效
标题翻译：用于制造包括自对准栅极的MESFET的方法
公开(公告)号：US4889827A
公开(公告)日：1989-12-26
申请号：US247662
申请日：1988-09-22
申请人： Josef Willer
发明人： Josef Willer
IPC分类号： H01L21/302 , H01L21/28 , H01L21/285 , H01L21/3065 , H01L21/338 , H01L29/812
CPC分类号： H01L29/66863 , H01L21/28587 , Y10S148/139 , Y10S148/14 , Y10S148/168
摘要： A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.
摘要翻译：一种用于制造MESFET的方法，包括相对于源极和漏极区域自对准的栅极以及相对于不同的金属化层的自对准栅极，由此第一金属层（21），第一介电层（31）），并且在载体衬底的掺杂之后施加第一漆掩模层。通过各向异性蚀刻形成在掺杂层（11）中产生外凹部的沟槽。第二电介质层被各向同性地沉积，并且除了间隔物（51/52）之外是各向异性再蚀刻，由此在掺杂层中产生内部凹部（双凹槽），最后施加栅极金属（22）。

60. 发明授权

US07796449B2 Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module 有权
标题翻译：集成电路，对集成电路的存储单元阵列进行编程的方法以及存储器模块
公开(公告)号：US07796449B2
公开(公告)日：2010-09-14
申请号：US12351023
申请日：2009-01-09
申请人： Josef Willer , Gert Koebernik
发明人： Josef Willer , Gert Koebernik
IPC分类号： G11C7/00
CPC分类号： G11C16/22
摘要： An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed.
摘要翻译：提供具有多个存储单元的存储单元布置的集成电路和存储单元布置控制器。存储单元布置控制器被配置为使得在对多个存储器单元中的至少一个存储单元进行编程期间，驱动与被编程的存储器单元相邻布置的至少一个存储单元，以将存储单元屏蔽到被编程。

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