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51. 发明申请

US20070001694A1 On-die real time leakage energy meter 审中-公开
标题翻译：片上实时泄漏电能表
公开(公告)号：US20070001694A1
公开(公告)日：2007-01-04
申请号：US11173147
申请日：2005-06-30
申请人： Sanjeev Jahagirdar , Jose Allarey , Varghese George
发明人： Sanjeev Jahagirdar , Jose Allarey , Varghese George
IPC分类号： G01R31/02
CPC分类号： G01R31/2891 , G01R21/02
摘要： A method includes measuring a temperature for a portion of an electronic component, determining the voltage being applied to the portion of the component, and determining a leakage power for the component portion based on a measured temperature and determined voltage for the portion of the component. The method also includes measuring a temperature for another portion of the component, determining the voltage being applied to the other component portion, and determining a leakage power for the other component portion based on the measured temperature and determined voltage for the other portion of the component. The method also includes summing the leakage power for the portion with the leakage power for the other portion of the component.
摘要翻译：一种方法包括测量电子部件的一部分的温度，确定施加到部件的该部分的电压，并且基于部件的该部分的测量温度和确定的电压来确定部件部分的泄漏功率。该方法还包括测量部件的另一部分的温度，确定施加到另一部件部分的电压，以及基于所测量的温度和组件的其它部分的确定电压来确定另一部件部分的泄漏功率。该方法还包括对具有部件的其他部分的泄漏功率的部分的泄漏功率求和。

52. 发明申请

US20060123154A1 Modular data transfer architecture 有权
标题翻译：模块化数据传输架构
公开(公告)号：US20060123154A1
公开(公告)日：2006-06-08
申请号：US11005926
申请日：2004-12-06
申请人： Varghese George
发明人： Varghese George
IPC分类号： G06F13/28
CPC分类号： G06F15/7825
摘要： A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block. The modular data transfer architecture further includes a plurality of internal modules support intra-chip communications. Each internal module has a plurality of initiator ports connected to target ports of other modules and a plurality of target ports connected to initiator ports of other modules. An internal port mapper for each internal module maps the global address to a certain internal module target port along the data path towards the second peripheral module.
摘要翻译：片上系统（SoC）集成电路包括多个计算块。模块化数据传输架构将用于片内通信的计算块互连。计算块包括发起者块和目标块，其中发起者块发起具有与目标块相关联的全局地址的数据通信。模块化数据传输架构包括第一外围模块，其具有连接到启动器块的发起端口以接收数据通信，以及具有连接到目标块的目标端口的第二外围模块。第一外围模块内的第一端口映射器将全局地址映射到沿第二外围模块的数据路径的第一外围模块目标端口。第二个外围模块中的第二个端口映射器将全局地址映射到连接到目标块的目标端口。模块化数据传输架构还包括多个内部模块支持片上通信。每个内部模块具有连接到其他模块的目标端口的多个启动器端口和连接到其他模块的启动器端口的多个目标端口。每个内部模块的内部端口映射器将全局地址映射到沿着数据路径的某个内部模块目标端口朝向第二个外围模块。

53. 发明申请

US20060036834A1 Trace reuse 审中-公开
标题翻译：跟踪重用
公开(公告)号：US20060036834A1
公开(公告)日：2006-02-16
申请号：US10917582
申请日：2004-08-13
申请人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
发明人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/325
摘要： A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.
摘要翻译：一种跟踪管理架构，可以在一个或多个重复轨迹中重新使用uops。更具体地，本发明的实施例涉及通过重复使用在微处理器的操作期间重复的迹线或迹线序列来防止对跟踪管理架构内的各种功能单元的多次访问的技术，从而避免由于多个跟踪而导致的性能差距高速缓存访问并增加可以在处理器内执行uop的速率。

54. 发明授权

US06785829B1 Multiple operating frequencies in a processor 有权
标题翻译：处理器中的多个工作频率
公开(公告)号：US06785829B1
公开(公告)日：2004-08-31
申请号：US09608160
申请日：2000-06-30
申请人： Varghese George , Robert L. Farrell
发明人： Varghese George , Robert L. Farrell
IPC分类号： G06F132
CPC分类号： G06F1/3296 , G06F1/08 , G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.
摘要翻译：一种功率控制电路，用于在单个电子设备的部分中调节工作频率和/或电源电压，同时在电子设备中的其它部分保持基本恒定的工作频率和/或电源电压的相应技术。这种控制是基于通过确定硬件产品是否连接到外部电源的采用电子设备的硬件产品的操作环境。结果，硬件产品中的电子设备能够在某些情况下以全频率和电压工作，并且在处理器的某些部分中以不降低的频率和/或电压工作，而在其他情况下不在其他部分。

55. 发明授权

US06748512B2 Method and apparatus for mapping address space of integrated programmable devices within host system memory 有权
标题翻译：用于映射主机系统存储器内集成可编程设备的地址空间的方法和装置
公开(公告)号：US06748512B2
公开(公告)日：2004-06-08
申请号：US09733875
申请日：2000-12-08
申请人： Deep Buch , Varghese George , Vladimir Pentkovski , Paul Zagacki , Edward Gamsaragan
发明人： Deep Buch , Varghese George , Vladimir Pentkovski , Paul Zagacki , Edward Gamsaragan
IPC分类号： G06F1208
CPC分类号： G06F12/0284 , G06F12/0835
摘要： A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
摘要翻译：本文描述了用于映射主机系统存储器内的集成可编程设备的地址空间的方法和装置。

56. 发明授权

US06502218B1 Deferred correction of a single bit storage error in a cache tag array 失效
标题翻译：缓存标记数组中单位存储错误的延迟校正
公开(公告)号：US06502218B1
公开(公告)日：2002-12-31
申请号：US09461243
申请日：1999-12-16
申请人： Varghese George , Michael Robert Mroczek
发明人： Varghese George , Michael Robert Mroczek
IPC分类号： G11C2900
CPC分类号： G06F11/1064
摘要： Methods and apparatus defer correction of an error in a tag entry of a cache tag array. An address of requested data, including an address tag field, can be received by a cache. A first hit indication based at least in part on a comparison of the address tag field and a first tag entry can be generated and result in outputting of a first data entry of a data array. An error in the tag entry can be detected, and the first data entry can be disregard based at least in part on the detected error.
摘要翻译：方法和装置延迟缓存标签数组的标签条目中的错误的校正。高速缓存可以接收包括地址标签字段在内的所请求数据的地址。可以生成至少部分地基于地址标签字段和第一标签条目的比较的第一命中指示，并且导致数据阵列的第一数据条目的输出。可以检测到标签条目中的错误，并且至少部分地基于检测到的错误可以忽略第一数据条目。

57. 发明授权

US09600413B2 Common platform for one-level memory architecture and two-level memory architecture 有权
公开(公告)号：US09600413B2
公开(公告)日：2017-03-21
申请号：US14140261
申请日：2013-12-24
申请人： Joydeep Ray , Varghese George , Inder M. Sodhi , Jeffrey R. Wilcox
发明人： Joydeep Ray , Varghese George , Inder M. Sodhi , Jeffrey R. Wilcox
IPC分类号： G06F12/00 , G06F12/06 , G06F12/02 , G11C5/04
CPC分类号： G06F3/061 , G06F1/3287 , G06F3/0634 , G06F3/0655 , G06F3/0688 , G06F12/0246 , G06F12/0638 , G06F12/0811 , G06F15/781 , G06F2212/283 , G06F2212/7206 , G11C5/04
摘要： Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.

58. 发明申请

US20160098075A1 Method And Apparatus For A Zero Voltage Processor Sleep State 审中-公开
公开(公告)号：US20160098075A1
公开(公告)日：2016-04-07
申请号：US14966708
申请日：2015-12-11
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

59. 发明申请

US20150178204A1 COMMON PLATFORM FOR ONE-LEVEL MEMORY ARCHITECTURE AND TWO-LEVEL MEMORY ARCHITECTURE 有权
标题翻译：一级存储器架构和两级存储器架构的通用平台
公开(公告)号：US20150178204A1
公开(公告)日：2015-06-25
申请号：US14140261
申请日：2013-12-24
申请人： Joydeep Ray , Varghese George , Inder M. Sodhi , Jeffrey R. Wilcox
发明人： Joydeep Ray , Varghese George , Inder M. Sodhi , Jeffrey R. Wilcox
IPC分类号： G06F12/08 , G06F12/06 , G06F12/02
CPC分类号： G06F3/061 , G06F1/3287 , G06F3/0634 , G06F3/0655 , G06F3/0688 , G06F12/0246 , G06F12/0638 , G06F12/0811 , G06F15/781 , G06F2212/283 , G06F2212/7206 , G11C5/04
摘要： Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.
摘要翻译：描述了在一个通用平台中的一级存储器（1LM）和两级存储器（2LM）配置的技术。处理器包括耦合到第一存储器设备的第一存储器接口，所述第一存储器设备位于处理器的外部封装处，以及耦合到位于处理器的封装外的第二存储器设备的第二存储器接口。处理器还包括耦合到第一存储器接口和第二存储器接口的多级存储器控制器（MLMC）。 MLMC包括第一配置和第二配置。第一存储器件是第一配置中的一级存储器（1LM）架构的随机存取存储器（RAM）。第一存储器件是第二配置中的二级存储器（2LM）架构的第一级RAM，并且第二存储器件是第二配置中的2LM架构的二级非易失性存储器（NVM）。

60. 发明申请

US20140281616A1 PLATFORM AGNOSTIC POWER MANAGEMENT 有权
标题翻译：平台电力管理
公开(公告)号：US20140281616A1
公开(公告)日：2014-09-18
申请号：US13799524
申请日：2013-03-13
申请人： Douglas Moran , Achmed Rumi Zahir , William Knolla , Hartej Singh , Vasudev Vasu Bibikar , Sanjeev Jahagirdar , Michael Klinglesmith , Irwin Vaz , Varghese George
发明人： Douglas Moran , Achmed Rumi Zahir , William Knolla , Hartej Singh , Vasudev Vasu Bibikar , Sanjeev Jahagirdar , Michael Klinglesmith , Irwin Vaz , Varghese George
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个功能块和中央功率控制器。至少一个功能块可以包括至少一个块组件和块功率逻辑。块功率逻辑可以是：接收在所述至少一个功能块中发起第一降低功率模式的第一请求，并且响应于所述第一请求，向中央功率控制器发送通知信号。中央功率控制器可以响应于通知信号：存储至少一个功能块的第一状态，并且启动至少一个功能块中的第一降低功率模式。描述和要求保护其他实施例。

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