专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20150206974A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150206974A1
公开(公告)日：2015-07-23
申请号：US14602660
申请日：2015-01-22
申请人： Ha-Jin Lim , Hyeong-Joon Kim , Nae-In Lee
发明人： Ha-Jin Lim , Hyeong-Joon Kim , Nae-In Lee
IPC分类号： H01L29/78 , H01L29/36 , H01L29/20
CPC分类号： H01L29/66818 , H01L21/02241 , H01L21/28264 , H01L21/823821 , H01L27/0924 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.
摘要翻译：半导体器件包括包含III族元素和V族元素的半导体衬底，以及在半导体衬底上的栅极结构。半导体衬底包括接触栅极结构的底表面的第一区域和设置在第一区域下方的第二区域。第一区域中的III族元素的浓度低于第一区域中的V族元素的浓度，并且第二区域中的III族元素的浓度基本上等于第二区域中的第V族元素的浓度地区。

52. 发明申请

US20150187763A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US20150187763A1
公开(公告)日：2015-07-02
申请号：US14489900
申请日：2014-09-18
申请人： Kug-Hwan Kim , Jong-Ho Lee , Woo-Hee Kim , Nae-In Lee
发明人： Kug-Hwan Kim , Jong-Ho Lee , Woo-Hee Kim , Nae-In Lee
IPC分类号： H01L27/088 , H01L29/49 , H01L29/51 , H01L29/423
CPC分类号： H01L21/823842 , H01L21/28202 , H01L21/823821 , H01L27/088 , H01L27/0922 , H01L27/0924 , H01L27/1104 , H01L27/1116 , H01L29/42364 , H01L29/4958 , H01L29/4966 , H01L29/518 , H01L29/66545
摘要： Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括包括第一至第四区域的衬底。此外，第一至第四栅极绝缘层分别在第一至第四区域上。在第一至第四栅极绝缘层中的功函数控制材料的量，第一至第四栅极绝缘层中的氮浓度和/或第一至第四栅极绝缘层的厚度在第一至第四栅极绝缘层之间变化。还提供了制造半导体器件的方法。

53. 发明申请

US20140141589A1 SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME 有权
标题翻译：包括压痕器的半导体器件及其形成方法
公开(公告)号：US20140141589A1
公开(公告)日：2014-05-22
申请号：US14033639
申请日：2013-09-23
申请人： Dong-Suk SHIN , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
发明人： Dong-Suk SHIN , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/02636 , H01L21/30604 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/045 , H01L29/0603 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66575 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
摘要翻译：提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。第二沟槽可以包括有源区的切口部分。

54. 发明授权

US07595253B2 Method of forming the semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US07595253B2
公开(公告)日：2009-09-29
申请号：US11797827
申请日：2007-05-08
申请人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： II-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

55. 发明授权

US07371633B2 Dielectric layer for semiconductor device and method of manufacturing the same 有权
标题翻译：用于半导体器件的介电层及其制造方法
公开(公告)号：US07371633B2
公开(公告)日：2008-05-13
申请号：US11027256
申请日：2004-12-30
申请人： Jong-Ho Lee , Nae-In Lee
发明人： Jong-Ho Lee , Nae-In Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02192 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7881 , H01L29/94
摘要： A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.
摘要翻译：半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。高k电介质层包括金属合金氧化物。

56. 发明申请

US20070262393A1 Semiconductor devices and methods of forming the same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070262393A1
公开(公告)日：2007-11-15
申请号：US11797827
申请日：2007-05-08
申请人： Il-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
发明人： Il-Young Yoon , Hong-Jae Shin , Nae-In Lee , Jae-Ouk Choo , Ja-Eung Koo
IPC分类号： H01L29/76 , H01L21/76 , H01L21/461 , H01L29/94 , H01L21/302 , H01L31/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.
摘要翻译：示例性实施例提供半导体器件及其形成方法。根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

57. 发明授权

US06881650B2 Method for forming SOI substrate 有权
标题翻译： SOI衬底的形成方法
公开(公告)号：US06881650B2
公开(公告)日：2005-04-19
申请号：US10307351
申请日：2002-12-02
申请人： Jung-Il Lee , Kazuyuki Fujihara , Nae-In Lee , Geum-Jong Bae , Hwa-Sung Rhee , Sang-su Kim
发明人： Jung-Il Lee , Kazuyuki Fujihara , Nae-In Lee , Geum-Jong Bae , Hwa-Sung Rhee , Sang-su Kim
IPC分类号： H01L21/205 , H01L21/02 , H01L21/20 , H01L21/30 , H01L21/46 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76254
摘要： A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.
摘要翻译：一种用于形成包括含有锗的SOI层和设置在SOI层上的应变硅层的SOI衬底的方法包括：使用外延生长方法在第一硅衬底上形成松弛的硅 - 锗层，并且形成多孔硅 - 锗层上。在多孔硅锗层上形成硅 - 锗外延层，在第二硅衬底上形成氧化物层，将形成氧化物层的第二硅衬底接合到第一硅衬底上，其中硅 - 锗外延形成层。去除层以暴露硅 - 锗外延层，并在其上形成应变硅外延层。多孔硅 - 锗层防止松散的硅 - 锗层的晶格缺陷转移到硅 - 锗外延层。因此，可以形成SOI层的硅 - 锗层和应变硅层，而没有缺陷。

58. 发明授权

US06881621B2 Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same 有权
标题翻译：制造具有蚀刻停止层的SOI衬底的方法，以及使用其制造SOI集成电路的方法
公开(公告)号：US06881621B2
公开(公告)日：2005-04-19
申请号：US10713216
申请日：2003-11-17
申请人： Tae-Hee Choe , Nae-In Lee , Geum-Jong Bae , Sang-Su Kim , Hwa-Sung Rhee
发明人： Tae-Hee Choe , Nae-In Lee , Geum-Jong Bae , Sang-Su Kim , Hwa-Sung Rhee
IPC分类号： H01L27/04 , H01L21/00 , H01L21/02 , H01L21/68 , H01L21/74 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/62 , H01L27/01 , H01L27/02 , H01L27/06 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/00 , H01L29/72 , H01L31/0392
CPC分类号： H01L21/6835 , H01L21/743 , H01L21/8221 , H01L21/84 , H01L27/0251 , H01L27/0688 , H01L27/1203 , H01L2221/68363 , H01L2924/30105
摘要： A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch stopping layer, which may be a silicon nitride layer, on a front surface of a supporting substrate; contacting the etch stopping layer with the buried oxide layer to bond the semiconductor substrate to the supporting substrate; and selectively removing the semiconductor substrate and the first semiconductor layer to expose the second semiconductor layer. The method may additionally include forming a buffer oxide layer between the supporting substrate and the etch stopping layer.
摘要翻译：制造SOI衬底的方法包括在半导体衬底的前表面上顺序地形成可以是多孔半导体层或气泡层的第一半导体层，第二半导体层和掩埋氧化物层，形成蚀刻停止层，其可以是氮化硅层;在支撑衬底的前表面上; 使所述蚀刻停止层与所述掩埋氧化物层接触以将所述半导体衬底接合到所述支撑衬底; 以及选择性地去除所述半导体衬底和所述第一半导体层以暴露所述第二半导体层。该方法还可以包括在支撑衬底和蚀刻停止层之间形成缓冲氧化物层。

59. 发明授权

US06815764B2 Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same 失效
标题翻译：具有两片门和自对准ONO的本地SONOS型结构及其制造方法
公开(公告)号：US06815764B2
公开(公告)日：2004-11-09
申请号：US10388631
申请日：2003-03-17
申请人： Geum-Jong Bae , Nae-In Lee , Sang Su Kim , Ki Chul Kim , Jin-Hee Kim , In-Wook Cho , Sung-Ho Kim , Kwang-Wook Koh
发明人： Geum-Jong Bae , Nae-In Lee , Sang Su Kim , Ki Chul Kim , Jin-Hee Kim , In-Wook Cho , Sung-Ho Kim , Kwang-Wook Koh
IPC分类号： H01L29792
CPC分类号： H01L29/792 , H01L29/7923 , Y10S438/954
摘要： A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.
摘要翻译：具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

60. 发明授权

US06806517B2 Flash memory having local SONOS structure using notched gate and manufacturing method thereof 失效
标题翻译：具有本地SONOS结构的闪存，使用缺口栅极及其制造方法
公开(公告)号：US06806517B2
公开(公告)日：2004-10-19
申请号：US10388427
申请日：2003-03-17
申请人： Sang Su Kim , Nae-In Lee , Geum-Jong Bae , Ki Chul Kim , Hwa Sung Rhee
发明人： Sang Su Kim , Nae-In Lee , Geum-Jong Bae , Ki Chul Kim , Hwa Sung Rhee
IPC分类号： H01L2710
CPC分类号： H01L29/4232 , H01L21/28114 , H01L21/28273 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate insulator leyer, having at least one notch; and at least one ONO wedge structure in the at least one notch, respectively, of the gate structure.
摘要翻译：缺口门SONOS晶体管包括：具有源/漏区的衬底; 在源/漏区之间的衬底上的栅极绝缘体层; 在所述栅极绝缘体雷管上具有至少一个凹口的缺口栅极结构; 以及分别在所述栅极结构的所述至少一个凹口中的至少一个ONO楔形结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式