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51. 发明授权

US08048753B2 Charging protection device 有权
标题翻译：充电保护装置
公开(公告)号：US08048753B2
公开(公告)日：2011-11-01
申请号：US12483737
申请日：2009-06-12
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

52. 发明申请

US20100314685A1 CHARGING PROTECTION DEVICE 有权
标题翻译：充电保护装置
公开(公告)号：US20100314685A1
公开(公告)日：2010-12-16
申请号：US12483737
申请日：2009-06-12
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L27/06 , H01L21/77
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

53. 发明授权

US07582493B2 Distinguishing between dopant and line width variation components 有权
标题翻译：区分掺杂剂和线宽变化组分
公开(公告)号：US07582493B2
公开(公告)日：2009-09-01
申请号：US11538872
申请日：2006-10-05
申请人： Akif Sultan , James F. Buller , David Donggang Wu
发明人： Akif Sultan , James F. Buller , David Donggang Wu
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/14
摘要： A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.
摘要翻译：测试结构包括第一和第二多个晶体管。第一多个晶体管包括第一长度的栅电极。第二多个晶体管包括与第一长度不同的第二长度的栅电极。第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

54. 发明授权

US07208383B1 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US07208383B1
公开(公告)日：2007-04-24
申请号：US10284651
申请日：2002-10-30
申请人： Chad Weintraub , James F. Buller , Derick Wristers , Jon Cheek
发明人： Chad Weintraub , James F. Buller , Derick Wristers , Jon Cheek
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/66659
摘要： An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.
摘要翻译：具有减小的栅 - 漏重叠的绝缘栅场效应晶体管和用于制造绝缘栅场效应晶体管的方法。栅极结构形成在半导体衬底的主表面上。源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体材料中。源极延伸区域在栅极结构下方延伸，而漏极延伸区域与栅极结构横向间隔开。源极区域形成在半导体衬底中，并且在半导体衬底中形成漏极区域，其中源极区域和漏极区域与栅极结构横向间隔开。源极侧晕区形成在与源延伸区相邻的半导体衬底中。

55. 发明授权

US06967363B1 Lateral diode with multiple spacers 有权
标题翻译：具有多个间隔物的侧面二极管
公开(公告)号：US06967363B1
公开(公告)日：2005-11-22
申请号：US10676904
申请日：2003-10-01
申请人： James F. Buller
发明人： James F. Buller
IPC分类号： H01L27/06 , H01L27/08 , H01L29/739 , H01L29/76
CPC分类号： H01L29/7391 , H01L27/0629 , H01L27/0814
摘要： Various circuit devices, including diodes, and methods manufacturing therefor are provided. In one aspect, a method manufacturing is provided that includes forming a gate structure on a semiconductor portion of a substrate. The semiconductor portion has a first conductivity type. First and spacer structures are formed on opposite sides of the gate structure. A first impurity region of a second conductivity type is formed proximate the first spacer structure while the semiconductor portion lateral to the second spacer structure is masked. The first impurity region and the semiconductor portion define a junction. A width of the second spacer structure is reduced while the second spacer structure and the first impurity region are masked. A second impurity region of the first conductivity type is formed in the semiconductor portion proximate the second spacer structure. The method provides a diode with reduced series resistance.
摘要翻译：提供了包括二极管在内的各种电路装置及其制造方法。一方面，提供了一种制造方法，其包括在基板的半导体部分上形成栅极结构。半导体部分具有第一导电类型。第一和间隔结构形成在栅极结构的相对侧上。第二导电类型的第一杂质区形成在第一间隔结构附近，而第二间隔结构的侧面的半导体部分被掩蔽。第一杂质区和半导体部限定了结。第二间隔结构的宽度减小，而第二间隔结构和第一杂质区被掩蔽。在靠近第二间隔结构的半导体部分中形成第一导电类型的第二杂质区。该方法提供了具有降低的串联电阻的二极管。

56. 发明授权

US5849627A Bonded wafer processing with oxidative bonding 失效
标题翻译：具有氧化粘合的粘结晶片加工
公开(公告)号：US5849627A
公开(公告)日：1998-12-15
申请号：US430312
申请日：1995-04-28
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/316 , H01L21/762 , H01L21/30
CPC分类号： H01L21/2007 , H01L21/31654 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012
摘要： Low temperature wafer bonding using a chemically reacting material between wafers to form a bonded zone to bond two wafers together. Examples include silicon wafers with a silicon-oxidizing bonding liquid which also permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Silicon wafers also may use solid reactants which include deposited layers of metal and polysilicon to form silicide bonded zones. Oxidizers such as nitric acid may be used in the bonding liquid, and a bonding liquid may be used in conjunction with a solid bonding reactant. Dielectric layers on silicon wafers may be used when additional silicon is provided for the bonding reactions. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening and buried resistors.
摘要翻译：使用晶片之间的化学反应材料进行低温晶片接合，以形成将两个晶片结合在一起的结合区域。实例包括具有硅氧化粘合液体的硅晶片，其也允许引入辐射固化掺杂剂和作为粘合液体的组分的电活性掺杂剂。硅晶片还可以使用固体反应物，其包括金属和多晶硅的沉积层以形成硅化物结合区。可以在接合液中使用硝酸等氧化剂，结合液可以与固体键合反应物结合使用。当为粘合反应提供额外的硅时，可以使用硅晶片上的介电层。由这种接合晶片制造的集成电路可以具有掩埋层和辐射硬化和掩埋电阻。

57. 发明授权

US5569620A Bonded wafer processing with metal silicidation 失效
标题翻译：用金属硅化物粘结晶片加工
公开(公告)号：US5569620A
公开(公告)日：1996-10-29
申请号：US351933
申请日：1994-12-08
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/762 , H01L21/30 , H01L21/46
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S148/147
摘要： Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon-nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers.
摘要翻译：使用硅化物键形成反应的低温硅绝缘体晶片键合。与二氧化硅，金刚石，氮化硅等的介质隔离在沟槽隔离硅岛下产生埋入式电阻。由于接合硅化反应的低温，埋入的电介质可以是诸如金刚石的热敏膜。结合硅化物还在埋入金刚石层和处理晶片之间提供散热层，以获得良好的整体导热性。粘结硅化物也充当扩散阻挡层。

58. 发明授权

US5549786A Highly selective, highly uniform plasma etch process for spin-on glass 失效
标题翻译：用于旋涂玻璃的高选择性，高度均匀的等离子体蚀刻工艺
公开(公告)号：US5549786A
公开(公告)日：1996-08-27
申请号：US520758
申请日：1995-08-29
申请人： Stephen A. Jones , Shyam G. Garg , James F. Buller , Miguel Santana, Jr.
发明人： Stephen A. Jones , Shyam G. Garg , James F. Buller , Miguel Santana, Jr.
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116
摘要： An SOG plasma etch process is presented which is optimized for selectivity to PECVD silicon nitride. The present process also produces a uniform etch across the exposed surface of a semiconductor wafer. The etch process finds utility in dielectric-SOG-dielectric structures used as passivation layers. Silicon nitride is deposited using a PECVD technique to form the dielectric layers. By etching SOG at a faster rate than the rate at which it etches PECVD silicon nitride, the SOG plasma etch process removes enough of the SOG layer to prevent delamination problems associated with SOG layers interposed between dielectric layers without significantly reducing the thickness of the first dielectric layer. SOG remains only in troughs between closely-spaced interconnects and adjacent to the vertical steps between widely-spaced interconnects. Flow rates of He, CHF.sub.3, and N.sub.2 gases are established through a reaction chamber of a plasma etch system. The method includes pre-stabilizing steps, followed by an etch step, which is then followed by a post-stabilizing step and a particle removal or by-product flush step.
摘要翻译：提出了针对PECVD氮化硅的选择性优化的SOG等离子体蚀刻工艺。本方法还在半导体晶片的暴露表面上产生均匀蚀刻。蚀刻工艺在用作钝化层的介电SOG介电结构中发挥作用。使用PECVD技术沉积氮化硅以形成电介质层。通过以比其蚀刻PECVD氮化硅的速率更快的速率蚀刻SOG，SOG等离子体蚀刻工艺去除足够的SOG层，以防止与介于介电层之间的SOG层相关的分层问题，而不显着地减小第一电介质的厚度层。 SOG仅保留在紧密间隔的互连之间的槽中，并且与广泛间隔的互连之间的垂直台阶相邻。通过等离子体蚀刻系统的反应室建立He，CHF 3和N 2气体的流速。该方法包括预稳定步骤，随后是蚀刻步骤，然后进行后稳定化步骤和颗粒去除或副产物冲洗步骤。

59. 发明授权

US5387555A Bonded wafer processing with metal silicidation 失效
标题翻译：用金属硅化物粘结晶片加工
公开(公告)号：US5387555A
公开(公告)日：1995-02-07
申请号：US939786
申请日：1992-09-03
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/762 , H01L21/30 , H01L21/46
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S148/147
摘要： Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers. The silicide bonding takes place in the presense of a liquid oxidizer such as aqueous solution of HNO.sub.3 and H.sub.2 O.sub.2.
摘要翻译：使用硅化物键形成反应的低温硅绝缘体晶片键合。使用二氧化硅，金刚石，氮化硅等进行介质隔离，在沟槽隔离硅岛下产生掩埋电阻。由于接合硅化反应的低温，埋入的电介质可以是诸如金刚石的热敏膜。结合硅化物还在埋入金刚石层和处理晶片之间提供散热层，以获得良好的整体导热性。粘结硅化物也充当扩散阻挡层。硅化物结合发生在液体氧化剂如HNO 3和H 2 O 2的水溶液的存在之中。

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