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51. 发明授权

US07534726B2 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US07534726B2
公开(公告)日：2009-05-19
申请号：US11682632
申请日：2007-03-06
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L21/311
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

52. 发明授权

US07455076B2 Apparatus and method for controlling exhaust pressure in semiconductor manufacturing 失效
标题翻译：用于控制半导体制造中排气压力的装置和方法
公开(公告)号：US07455076B2
公开(公告)日：2008-11-25
申请号：US11032103
申请日：2005-01-11
申请人： Hyuk-Jin Kwon , Jong-Chul Park
发明人： Hyuk-Jin Kwon , Jong-Chul Park
IPC分类号： F16K3/18
CPC分类号： F16K3/34 , F16K1/222 , F16K1/223 , F16K3/0209 , F16K3/32 , F16K51/02 , Y10T137/7761 , Y10T137/8696 , Y10T137/87378
摘要： An apparatus and method for controlling exhaust produced by a reactive chamber is provided. The apparatus for controlling exhaust may include, for example, a valve body having an exhaust hole for the exhaust to pass through, and may include a first and second valve which regulate the opening and/or the closing of the exhaust hole. A control device may control the operation of the first and second valves based on the internal pressure of the reactive chamber.
摘要翻译：提供了一种用于控制由反应室产生的排气的装置和方法。用于控制排气的装置可以包括例如具有用于排气通过的排气孔的阀体，并且可以包括调节排气孔的打开和/或关闭的第一和第二阀。控制装置可以基于反应室的内部压力来控制第一和第二阀的操作。

53. 发明授权

US07326619B2 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US07326619B2
公开(公告)日：2008-02-05
申请号：US10902642
申请日：2004-07-28
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

54. 发明授权

US07312117B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07312117B2
公开(公告)日：2007-12-25
申请号：US11193788
申请日：2005-07-28
申请人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
发明人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.
摘要翻译：半导体器件包括在限定在衬底上的有源区上沿第一方向延伸的字线结构。第一和第二接触垫形成在字线结构两侧的有源区上。位线结构电连接到第一接触焊盘并沿基本垂直于第一方向的第二方向延伸。在具有位线结构的基板上形成绝缘层结构。存储节点接触插头通过绝缘层结构电连接到第二接触垫。作为电容器的一部分的存储节点电极形成在存储节点接触插头上。存储节点接触插头具有下部和具有比下部的宽度宽的上部，其垂直方向垂直于第一和第二方向。

55. 发明授权

US07235445B2 Methods of forming device with recessed gate electrodes 有权
标题翻译：具有凹陷栅电极的器件形成方法
公开(公告)号：US07235445B2
公开(公告)日：2007-06-26
申请号：US11148760
申请日：2005-06-09
申请人： Jae-Kyu Ha , Jong-Chul Park
发明人： Jae-Kyu Ha , Jong-Chul Park
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876
摘要： Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active region. A hard mask layer is formed with a substantially planar upper surface on the field region and the active region. The hard mask layer is partially etched to form a hard mask pattern that exposes at least a portion of the active region. The substrate is partially etched in the active region using the hard mask pattern as an etching mask to form a gate trench. A recessed gate electrode if formed on the substrate in the gate trench.
摘要翻译：提供了用于形成诸如半导体器件的器件的方法。定义了场区域和衬底的有源区域，其中场区域具有远离衬底延伸的上表面并且高于有源区域的上表面。硬掩模层在场区域和有源区域上形成有基本平坦的上表面。硬掩模层被部分蚀刻以形成暴露至少一部分有源区的硬掩模图案。使用硬掩模图案作为蚀刻掩模在有源区中部分地蚀刻衬底以形成栅极沟槽。如果形成在栅极沟槽中的衬底上的凹陷栅电极。

56. 发明申请

US20060063324A1 Method of manufacturing a semiconductor device 失效
公开(公告)号：US20060063324A1
公开(公告)日：2006-03-23
申请号：US11173189
申请日：2005-06-30
申请人： Jong-Chul Park , Sang-Sup Jeong
发明人： Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L27/10894
摘要： In an embodiment, a simplified method of manufacturing a semiconductor device reduces a step between cell and peripheral areas. First and second openings are formed through a plurality of thin layers including a support layer on a substrate. A storage electrode and a guide ring are formed on sidewalls and bottoms of the first and second openings, respectively. A support pattern is formed so that the support layer in the cell area is partially etched and the support layer in the peripheral area remains un-etched, thus the support pattern supports and surrounds the storage electrodes adjacent to each other in the cell area and prevents an etching of a layer underlying the support layer in the peripheral area. A dielectric layer and a plate electrode are formed on the storage electrode to complete a semiconductor device with the reduced step.

57. 发明申请

US20060022256A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060022256A1
公开(公告)日：2006-02-02
申请号：US11193788
申请日：2005-07-28
申请人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
发明人： Doo-Young Lee , Yoo-Chul Kong , Jong-Chul Park , Sang-Sup Jeong
IPC分类号： H01L29/788
CPC分类号： H01L28/91 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.
摘要翻译：半导体器件包括在限定在衬底上的有源区上沿第一方向延伸的字线结构。第一和第二接触垫形成在字线结构两侧的有源区上。位线结构电连接到第一接触焊盘并沿基本垂直于第一方向的第二方向延伸。在具有位线结构的基板上形成绝缘层结构。存储节点接触插头通过绝缘层结构电连接到第二接触垫。作为电容器的一部分的存储节点电极形成在存储节点接触插头上。存储节点接触插头具有下部部分和具有比下部部分宽的宽度的上部部分，垂直方向垂直于第一和第二方向。

58. 发明申请

US20050263484A1 Adjustable shielding plate for adjusting an etching area of a semiconductor wafer and related apparatus and methods 失效
标题翻译：用于调整半导体晶片的蚀刻区域的可调节屏蔽板及相关装置和方法
公开(公告)号：US20050263484A1
公开(公告)日：2005-12-01
申请号：US11119490
申请日：2005-04-29
申请人： Jong-Chul Park , Sang-sup Jeong
发明人： Jong-Chul Park , Sang-sup Jeong
IPC分类号： H01L21/3065 , G01L21/30 , H01J37/32 , H01L21/00 , H01L21/02
CPC分类号： H01J37/32623 , H01J2237/334 , H01L21/02087 , H01L21/67069
摘要： An apparatus for adjusting an etching area of a semiconductor wafer includes an adjustable shielding plate. The adjustable shielding plate includes a plurality of shielding members. Each of the plurality of shielding members are movable between a first position configured to shield a portion of a semiconductor wafer from an etching gas and a second position configured to expose an unshielded etching portion of the semiconductor wafer to the etching gas.
摘要翻译：用于调整半导体晶片的蚀刻区域的装置包括可调节屏蔽板。可调节屏蔽板包括多个屏蔽构件。多个屏蔽部件中的每一个可以在构造成从蚀刻气体屏蔽半导体晶片的一部分的第一位置和被配置为将半导体晶片的非屏蔽蚀刻部分暴露于蚀刻气体的第二位置之间移动。

59. 发明授权

US5816097A Position control apparatus for gyroscope 失效
标题翻译：陀螺仪位置控制装置
公开(公告)号：US5816097A
公开(公告)日：1998-10-06
申请号：US781981
申请日：1996-12-27
申请人： Jong-Chul Park
发明人： Jong-Chul Park
IPC分类号： G01C19/30 , G01C19/04 , G01C19/02 , F16M13/00 , G05G11/00
CPC分类号： G01C19/04 , Y10T74/12 , Y10T74/1293 , Y10T74/20378
摘要： A position control apparatus for a gyroscope mechanically controls a setting position of the gyroscope. The position control apparatus for a gyroscope includes a circular mount for adjusting a setting position of the gyroscope in a predetermined direction, a plurality of tightening screws for fixing the gyroscope to the circular mount by way of several through holes, a plurality of locking screws for fixing the circular mount by way of several open holes formed in a supporting mechanism, a plurality of adjusting screws for adjusting the set position of the gyroscope in a up or down direction, and an adjusting flute prepared at an end of the circular mount, for adjusting the set position of the gyroscope in an axial direction.
摘要翻译：陀螺仪的位置控制装置机械地控制陀螺仪的设定位置。用于陀螺仪的位置控制装置包括用于调整陀螺仪沿预定方向的设置位置的圆形安装座，用于通过多个通孔将陀螺仪固定到圆形安装座的多个紧固螺钉，多个用于通过形成在支撑机构中的几个开孔固定圆形安装座，用于调节陀螺仪在上下方向上的设定位置的多个调节螺钉以及在圆形安装件的端部准备的调节槽，用于在轴向上调整陀螺仪的设定位置。

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