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51. 发明申请

US20120309155A1 SEMICONDUCTOR PROCESS 审中-公开
标题翻译：半导体工艺
公开(公告)号：US20120309155A1
公开(公告)日：2012-12-06
申请号：US13152283
申请日：2011-06-03
申请人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8239
CPC分类号： H01L27/1052 , H01L21/76816 , H01L21/76897
摘要： A semiconductor process is provided. A substrate is provided, gates each including a silicon layer, a silicide layer and a cap layer are formed thereon, and doped regions are formed at two sides of each gate. An insulating layer is formed to cover a memory region and a periphery region. First contact holes are formed in the insulating layer in the memory region, and each first contact hole is disposed between the two adjacent gates and exposes the doped region. A contact plug is formed in each first contact hole to electrically connect the doped region. A patterned mask layer is formed on the substrate to cover the memory region and expose a portion of the periphery region. Using the patterned mask layer as a mask, second and third contact holes are formed in the insulating layer in the periphery region, to expose the silicide layer and the doped region.
摘要翻译：提供半导体工艺。提供衬底，在其上形成各自包括硅层，硅化物层和覆盖层的栅极，并且在每个栅极的两侧形成掺杂区域。形成绝缘层以覆盖存储区域和周边区域。第一接触孔形成在存储区域中的绝缘层中，并且每个第一接触孔设置在两个相邻栅极之间并且暴露掺杂区域。在每个第一接触孔中形成接触插塞以电连接掺杂区域。在基板上形成图案化掩模层以覆盖存储区域并暴露外围区域的一部分。使用图案化掩模层作为掩模，在外围区域的绝缘层中形成第二和第三接触孔，以暴露硅化物层和掺杂区域。

52. 发明申请

US20120298992A1 TEST LAYOUT STRUCTURE 审中-公开
标题翻译：测试布局结构
公开(公告)号：US20120298992A1
公开(公告)日：2012-11-29
申请号：US13117126
申请日：2011-05-26
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544
CPC分类号： H01L22/34
摘要： A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other.
摘要翻译：测试布局结构包括基板，第一高度的第一氧化物区域，第二高度的第二氧化物区域，多个边界区域和测试布局图案。第一氧化物区域设置在基板上。第二氧化物区域也设置在衬底上并与第一氧化物区域相邻。第一高度与第二高度大致不同。多个边界区域设置在第一氧化物区域和第二氧化物区域之间。测试布局图案包括多个单独的部分。测试区域设置在彼此平行的两个相邻的单独部分之间。

53. 发明申请

US20120293196A1 TEST KEY STRUCTURE FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT AND TESTING METHOD THEREOF 审中-公开
标题翻译：用于监控门电导体深度偏差的测试关键结构及其测试方法
公开(公告)号：US20120293196A1
公开(公告)日：2012-11-22
申请号：US13111714
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/26
CPC分类号： G01R31/2644 , G01R31/2884
摘要： The disclosure provides a test key structure for monitoring gate conductor to deep trench misalignment and a testing method thereof. The test key structure for monitoring gate conductor to deep trench misalignment includes: a deep trench capacitor structure comprising a plurality of parallel deep trench capacitor lines and a deep trench capacitor connect; a buried strap out-diffusion adjacent to a first side of the deep trench capacitor line; a first gate conductor structure comprising a plurality of parallel first gate conductor lines and a first gate conductor connect, wherein each first gate conductor line is disposed directly over the corresponding deep trench capacitor line; and a second gate conductor structure comprising a plurality of parallel second gate conductor lines and a second gate conductor connect, wherein the first gate conductor lines are electrically connected to each other via the second gate conductor connect, and wherein the first gate conductor lines and the second gate conductor lines are parallel to each other, and the first gate conductor lines and the second gate conductor lines are arranged alternately.
摘要翻译：本公开提供了用于监视栅极导体到深沟槽未对准的测试键结构及其测试方法。用于监控栅极导体到深沟槽未对准的测试键结构包括：深沟槽电容器结构，其包括多个平行深沟槽电容器线和深沟槽电容器连接; 邻近深沟槽电容器线的第一侧的掩埋带外扩散; 包括多个平行的第一栅极导体线和第一栅极导体连接的第一栅极导体结构，其中每个第一栅极导线直接设置在相应的深沟槽电容器线上方; 以及包括多个平行的第二栅极导体线和第二栅极导体连接的第二栅极导体结构，其中所述第一栅极导体线经由所述第二栅极导体连接彼此电连接，并且其中所述第一栅极导体线和第二栅极导体线彼此平行，并且第一栅极导体线和第二栅极导体线交替布置。

54. 发明申请

US20120289050A1 METHOD OF ETCHING TRENCHES IN A SEMICONDUCTOR SUBSTRATE UTILIZING PULSED AND FLUOROCARBON-FREE PLASMA 审中-公开
标题翻译：在利用脉冲和无氟等离子体的半导体衬底中蚀刻铁素体的方法
公开(公告)号：US20120289050A1
公开(公告)日：2012-11-15
申请号：US13103113
申请日：2011-05-09
申请人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chang-Ming Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/3065
CPC分类号： H01L27/10844 , H01L21/3065 , H01L21/3081 , H01L21/76229
摘要： A method of etching trenches in a semiconductor substrate. A patterned hard mask is formed over a semiconductor substrate. Using the patterned hard mask as an etching mask, a plasma etching process is then carried out to etch trenches into the semiconductor substrate not covered by the patterned hard mask, wherein the plasma etching process employs a fluorocarbon-free plasma etching chemistry and is performed under a plasma pulse output mode.
摘要翻译：蚀刻半导体衬底中的沟槽的方法。在半导体衬底上形成图案化的硬掩模。使用图案化的硬掩模作为蚀刻掩模，然后执行等离子体蚀刻工艺以将沟槽蚀刻到未被图案化硬掩模覆盖的半导体衬底中，其中等离子体蚀刻工艺采用无碳氟化合物等离子体蚀刻化学法，并且在等离子体脉冲输出模式。

55. 发明申请

US20120288683A1 PROTUBERANT STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：制备该方法的制备方法及方法
公开(公告)号：US20120288683A1
公开(公告)日：2012-11-15
申请号：US13104943
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B32B3/00 , B05D5/02
CPC分类号： H01L21/0338 , B81B2203/0361 , B81B2203/0384 , B81C1/00103 , H01L21/0337 , H01L21/28123 , H01L29/42376 , Y10T428/24612
摘要： The protuberant structure of the present invention includes a substrate and a protrusion disposed on the substrate. The protrusion has a top side, a bottom side and a tapered side wall disposed between the top side and the bottom side. The top side has an extremely small top width which is not greater than 32 nm.
摘要翻译：本发明的突出结构包括基板和设置在基板上的突起。突起具有设置在顶侧和底侧之间的顶侧，底侧和锥形侧壁。顶侧具有不大于32nm的非常小的顶部宽度。

56. 发明申请

US20120286352A1 TRENCH MOS STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： TRENCH MOS结构及其制造方法
公开(公告)号：US20120286352A1
公开(公告)日：2012-11-15
申请号：US13104924
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
摘要翻译：提供沟槽MOS结构。沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。沟槽设置在外延层中。栅极隔离覆盖沟槽的内壁。沟槽栅设置在沟槽中并且具有第一导电类型。保护环具有第二导电类型并且设置在外延层内。加强结构具有电绝缘材料并且设置在保护环内。

57. 发明申请

US20120285483A1 METHOD OF CLEANING A WAFER 审中-公开
标题翻译：清洗方法
公开(公告)号：US20120285483A1
公开(公告)日：2012-11-15
申请号：US13106816
申请日：2011-05-12
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B1/00
CPC分类号： B08B3/02 , B08B2203/0288 , H01L21/02068 , H01L21/67028
摘要： A method of cleaning a wafer is disclosed in the present invention. This method is particularly suitable for cleaning the metal layer on the wafer. First, a wafer having a metal layer is loaded into a cleaning chamber, wherein a plurality of particles are inlaid in a surface of the metal layer. Later, a first clean stage is performed to rinse the wafer by jetted liquid introduced with megasonic energy. After the first clean stage, a second clean stage is performed to scrub the wafer. Finally, the wafer is dried.
摘要翻译：在本发明中公开了一种清洁晶片的方法。该方法特别适用于清洗晶片上的金属层。首先，将具有金属层的晶片装载到清洁室中，其中多个颗粒镶嵌在金属层的表面中。之后，进行第一个清洁阶段，用引入了超声波能量的喷射液冲洗晶片。在第一个清洁阶段之后，执行第二个清洁阶段来擦洗晶片。最后，将晶片干燥。

58. 发明申请

US20120276707A1 METHOD FOR FORMING TRENCH ISOLATION 审中-公开
标题翻译：形成分离分离方法
公开(公告)号：US20120276707A1
公开(公告)日：2012-11-01
申请号：US13096985
申请日：2011-04-28
申请人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
发明人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/31
CPC分类号： H01L21/76224
摘要： A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench.
摘要翻译：公开了一种用于形成沟槽隔离的方法，包括：提供包括沟槽的衬底，在沟槽中形成多晶硅层，并对衬底进行处理工艺以将多晶硅层转化为隔离层，其中处理工艺为对于沟槽的相对侧壁上的隔离层进行微调，以使其彼此接触以使隔离层填充沟槽。

59. 发明申请

US20120264359A1 MEMBRANE 审中-公开
标题翻译：膜
公开(公告)号：US20120264359A1
公开(公告)日：2012-10-18
申请号：US13085489
申请日：2011-04-13
申请人： Chien-Mao Liao , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chien-Mao Liao , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B24B7/22
CPC分类号： B24B37/30
摘要： A membrane is suitable to be mounted on a polishing head of a chemical mechanical polishing apparatus and includes a main portion and an edge portion. The edge portion is located at an edge of the main portion, wherein a first included angle between the main portion and the edge portion is an obtuse angle.
摘要翻译：膜适于安装在化学机械抛光装置的抛光头上，并且包括主要部分和边缘部分。边缘部分位于主要部分的边缘处，其中主要部分和边缘部分之间的第一夹角是钝角。

60. 发明申请

US20120256279A1 METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR 有权
标题翻译：门工作功能调整和金属栅极晶体管的方法
公开(公告)号：US20120256279A1
公开(公告)日：2012-10-11
申请号：US13081505
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/265 , H01L21/26586 , H01L21/28079 , H01L21/28105 , H01L29/495 , H01L29/66575 , H01L29/66795 , H01L29/78 , H01L29/7856
摘要： A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.
摘要翻译：门功功能调整方法包括以下步骤。首先，提供基板，其中金属栅极设置在基板上，源极掺杂区域和漏极掺杂区域设置在金属栅极的相对位置处的基板中，其中金属栅极被分成相邻的源极侧到源极掺杂区域和与漏极掺杂区域相邻的漏极侧。然后，形成掩模层以覆盖源极掺杂区域和漏极掺杂区域。之后，进行注入工艺以将氮注入到金属栅中，以使源极侧的第一氮浓度高于漏极侧的第二氮浓度。最后，去除掩模层。

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