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51. 发明申请

US20080034174A1 Non-volatile memory storage systems for phased garbage collection 有权
公开(公告)号：US20080034174A1
公开(公告)日：2008-02-07
申请号：US11499598
申请日：2006-08-04
申请人： Shai Traister , Jason Lin
发明人： Shai Traister , Jason Lin
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7205
摘要： A non-volatile memory storage system is provided. The non-volatile memory storage system includes a memory configured to store a storage system firmware and a non-volatile memory cell array configured to maintain a buffer. A processor in communication with the memory and the non-volatile memory cell array also is included in the non-volatile memory storage system. Here, the processor is configured to execute the storage system firmware stored in the memory. The storage system firmware comprises program instructions for receiving a write command to write data to the non-volatile memory cell array. The write command is allocated a timeout period to complete an execution of the write command. The storage system firmware also comprises program instructions for performing a portion of a garbage collection operation within the timeout period and for storing the data in the buffer.

52. 发明申请

US20120005405A1 Pre-Emptive Garbage Collection of Memory Blocks 有权
标题翻译：内存块预先的垃圾收集
公开(公告)号：US20120005405A1
公开(公告)日：2012-01-05
申请号：US12828241
申请日：2010-06-30
申请人： William Wu , Shai Traister , Jianmin Huang , Neil David Hutchison , Steven Sprouse
发明人： William Wu , Shai Traister , Jianmin Huang , Neil David Hutchison , Steven Sprouse
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0253
摘要： A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system.
摘要翻译：一种方法和系统在存储器设备中的更新块上优先地执行强制量的垃圾回收操作。监视和调整某些数据写入所需的垃圾回收量，以便在必要时与强制量匹配。可以基于它们最近的使用或所需的垃圾收集量来选择更新块。另一种方法和系统可以将关于更新块的控制信息存储在临时存储区域中，以便利用更多数量的更新块。通过速度等级测试测量的顺序写入性能可以通过使用此方法和系统进行优化。

53. 发明申请

US20100174869A1 MAPPING ADDRESS TABLE MAINTENANCE IN A MEMORY DEVICE 有权
标题翻译：映射地址表维护存储器件
公开(公告)号：US20100174869A1
公开(公告)日：2010-07-08
申请号：US12348782
申请日：2009-01-05
申请人： Sergey Anatolievich Gorobets , Alexander Paley , Eugene Zilberman , Alan David Bennett , Shai Traister
发明人： Sergey Anatolievich Gorobets , Alexander Paley , Eugene Zilberman , Alan David Bennett , Shai Traister
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F12/1027 , G06F2212/1016 , G06F2212/7201 , G06F2212/7205
摘要： A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.
摘要翻译：方法和系统维护用于将逻辑组映射到存储器设备中的物理地址的地址表。该方法包括接收在地址表中设置条目的请求，并根据高速缓存中的条目的存在以及高速缓存是否满足冲洗阈值标准来选择和刷新地址表高速缓存中的条目。刷新的条目包括小于地址表缓存的最大容量。刷新阈值标准包括地址表缓存是否满或页面是否超过已更改条目的阈值。地址表和/或地址表缓存可以存储在非易失性存储器和/或随机存取存储器中。由于将地址表缓存部分刷新到地址表所需的写入操作次数和时间减少，因此可能会导致使用此方法和系统的性能提高。

54. 发明申请

US20100174847A1 Non-Volatile Memory and Method With Write Cache Partition Management Methods 有权
标题翻译：非易失性存储器和写缓存分区管理方法
公开(公告)号：US20100174847A1
公开(公告)日：2010-07-08
申请号：US12348899
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/224 , G06F2212/7203 , G06F2212/7204
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。优选地，分配耐力计数高于平均值的块。数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。

55. 发明申请

US20100146186A1 Program Control of a non-volatile memory 有权
标题翻译：非易失性存储器的程序控制
公开(公告)号：US20100146186A1
公开(公告)日：2010-06-10
申请号：US12316159
申请日：2008-12-10
申请人： Shai Traister , Jonathan Hsu
发明人： Shai Traister , Jonathan Hsu
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203 , G11C11/5628 , G11C2211/5643
摘要： A method of storing data onto a non-volatile memory includes receiving, from a host, first data that is originally assigned to a first storage area, programming the first data to a second storage area, receiving second data from the host, and while receiving the second data from the host, programming, to the first storage area, the first data that has been programmed to the second storage area, wherein the second data is received from the host simultaneously with the first data being programmed to the first storage area. The second storage area is capable of having data stored thereon faster than the first storage area.
摘要翻译：将数据存储到非易失性存储器的方法包括：从主机接收最初分配给第一存储区域的第一数据，将第一数据编程到第二存储区域，从主机接收第二数据，以及在接收时所述第二数据从所述主机，编程到所述第一存储区域，所述第一数据已被编程到所述第二存储区域，其中所述第二数据从所述主机接收，所述第一数据被编程到所述第一存储区域。第二存储区域能够在其上存储比第一存储区域更快的数据。

56. 发明授权

US07441071B2 Memory systems for phased garbage collection using phased garbage collection block or scratch pad block as a buffer 有权
标题翻译：使用分阶段垃圾收集块或便笺块作为缓冲区的分阶段垃圾收集的内存系统
公开(公告)号：US07441071B2
公开(公告)日：2008-10-21
申请号：US11541012
申请日：2006-09-28
申请人： Shai Traister , Jason Lin
发明人： Shai Traister , Jason Lin
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a memory configured to store a storage system firmware and a non-volatile memory cell array. Additionally included is a processor in communication with the memory and the non-volatile memory cell array. The processor is configured to execute the storage system firmware stored in the memory. The storage system firmware includes program instructions for receiving a write command to write a plurality of data to the non-volatile memory cell array. The write command is allocated a timeout period to complete an execution of the write command. Additionally included are program instructions for asserting a busy signal, performing a portion of a garbage collection operation for a garbage collection time period, writing the data to a block, and releasing the busy signal before the timeout period.
摘要翻译：提供了非易失性存储器存储系统。非易失性存储器存储系统包括被配置为存储存储系统固件和非易失性存储单元阵列的存储器。另外包括与存储器和非易失性存储单元阵列通信的处理器。处理器被配置为执行存储在存储器中的存储系统固件。存储系统固件包括用于接收写入命令以写入多个数据到非易失性存储器单元阵列的程序指令。写命令被分配一个超时周期以完成写入命令的执行。另外包括用于断言忙信号的程序指令，执行垃圾收集时间段的垃圾收集操作的一部分，将数据写入块，以及在超时时段之前释放忙信号。

57. 发明申请

US20080235465A1 Systems for conversion of update blocks based on association with host file management data structures 审中-公开
标题翻译：基于与主机文件管理数据结构的关联来更新更新块的系统
公开(公告)号：US20080235465A1
公开(公告)日：2008-09-25
申请号：US11725745
申请日：2007-03-19
申请人： Bum Suck So , Shai Traister
发明人： Bum Suck So , Shai Traister
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/064 , G06F3/0679 , G06F2212/7202
摘要： A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. Here, the processor is configured to receive a write command to write data, where the write command comprises a logical address associated with the data. The processor is further configured to allocate a chaotic update block if the logical address is associated with a host file management data structure. After the allocation, the data are written to the chaotic update block.
摘要翻译：提供了非易失性存储器存储系统。非易失性存储器存储系统包括非易失性存储单元阵列和与非易失性存储单元阵列通信的处理器。这里，处理器被配置为接收写入命令以写入数据，其中写入命令包括与数据相关联的逻辑地址。处理器还被配置为如果逻辑地址与主机文件管理数据结构相关联，则分配混沌更新块。在分配之后，数据被写入混沌更新块。

58. 发明申请

US20080235464A1 System for conversion of update blocks based on comparison with a threshold size 审中-公开
标题翻译：基于与阈值大小的比较来更新更新块的系统
公开(公告)号：US20080235464A1
公开(公告)日：2008-09-25
申请号：US11725670
申请日：2007-03-19
申请人： Shai Traister
发明人： Shai Traister
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. The processor is configured to receive a write command to write data following a previous write command. Here, the write command and the previous write command have a discontinuity in logical addresses, where the discontinuity in logical addresses defines a gap between a logical address of the write command and a logical address of the previous write command. A sequential update block and preexisting data associated with the sequential update block are provided. The processor is further configured to compare the gap with a threshold size and write the data to the sequential update block if the gap is less than the threshold size.
摘要翻译：提供了非易失性存储器存储系统。非易失性存储器存储系统包括非易失性存储单元阵列和与非易失性存储单元阵列通信的处理器。处理器被配置为接收写入命令以在先前写入命令之后写入数据。这里，写入命令和先前的写入命令在逻辑地址中具有不连续性，其中逻辑地址中的不连续性定义了写入命令的逻辑地址与先前写入命令的逻辑地址之间的间隙。提供顺序更新块和与顺序更新块相关联的预先存在的数据。处理器还被配置为将间隙与阈值尺寸进行比较，并且如果间隙小于阈值尺寸，则将数据写入顺序更新块。

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