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51. 发明授权

US07728373B2 DRAM device with cell epitaxial layers partially overlap buried cell gate electrode 有权
标题翻译：具有电池外延层的DRAM器件部分地覆盖埋电池栅电极
公开(公告)号：US07728373B2
公开(公告)日：2010-06-01
申请号：US11705109
申请日：2007-02-12
申请人： Hyeoung-Won Seo , Jae-Man Yoon , Kang-Yoon Lee , Bong-Soo Kim
发明人： Hyeoung-Won Seo , Jae-Man Yoon , Kang-Yoon Lee , Bong-Soo Kim
IPC分类号： H01L21/2842
CPC分类号： H01L29/66628 , H01L27/10814 , H01L27/10876 , H01L27/10894 , H01L29/7834
摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
摘要翻译：半导体器件可以包括具有电池有源区的衬底。可以在电池活性区域中形成电池栅电极。单元栅极覆盖层可以形成在单元栅电极上。至少两个电池外延层可以形成在电池有源区上。至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。电池杂质区域可以设置在电池活性区域中。电池杂质区域可以对应于至少两个电池外延层中的相应一个。

52. 发明授权

US07665206B2 Printed circuit board and manufacturing method thereof 失效
标题翻译：印刷电路板及其制造方法
公开(公告)号：US07665206B2
公开(公告)日：2010-02-23
申请号：US12007127
申请日：2008-01-07
申请人： Kwang-Soo Park , Dong-Sam You , Bong-Soo Kim , Myung-Gun Chong , Dae-Jung Byun
发明人： Kwang-Soo Park , Dong-Sam You , Bong-Soo Kim , Myung-Gun Chong , Dae-Jung Byun
IPC分类号： H05K3/00 , H05K1/00 , H05K1/03
CPC分类号： H05K1/183 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H05K1/0298 , H05K3/0032 , H05K3/0044 , H05K2201/0919 , H05K2201/09845 , H05K2201/09972 , H05K2203/0228 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49133 , Y10T29/49156 , H01L2224/0401
摘要： A printed circuit board and a method of manufacturing a printed circuit board are disclosed. Using a method of manufacturing a printed circuit board, which includes: forming a multilayer board by alternately stacking circuit pattern layers and insulation layers such that a predetermined thickness of a partial area has only insulation layers stacked therein; and removing insulation layers from the partial area of the multilayer board, a printed circuit board can be manufactured that is suitable for a slim module.
摘要翻译：公开了印刷电路板和制造印刷电路板的方法。使用制造印刷电路板的方法，其包括：通过交替堆叠电路图案层和绝缘层来形成多层板，使得部分区域的预定厚度仅具有堆叠在其中的绝缘层; 并且从多层板的部分区域去除绝缘层，可以制造适合于纤薄模块的印刷电路板。

53. 发明授权

US07619281B2 Semiconductor device having buried gate line and method of fabricating the same 有权
标题翻译：具有掩埋栅极线的半导体器件及其制造方法
公开(公告)号：US07619281B2
公开(公告)日：2009-11-17
申请号：US11797137
申请日：2007-05-01
申请人： Hyeoung-Won Seo , Young-Woong Son , Kang-Yoon Lee , Bong-Soo Kim
发明人： Hyeoung-Won Seo , Young-Woong Son , Kang-Yoon Lee , Bong-Soo Kim
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7851 , H01L27/10826 , H01L27/10891 , H01L27/24 , H01L29/1037 , H01L29/4236 , H01L29/66621 , H01L29/66795 , H01L29/7853
摘要： A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.
摘要翻译：公开了具有具有成形栅极沟槽的掩埋栅极线的半导体器件及其制造方法。半导体器件包括设置在半导体衬底中以限定多表面有源区/沟道的沟槽隔离层。延伸到沟槽隔离层的栅极线填充栅极沟槽的一部分。栅极沟槽形成有一系列凹陷以容纳通道中的峰值。凹陷/峰值的组合用于增加通道的有效面积，从而能够在不增加其宽度的情况下形成更小的沟道半导体器件。

54. 发明申请

US20090199395A1 SIDE-DOCKING TYPE TEST HANDLER AND APPARATUS FOR TRANSFERRING TEST TRAY FOR SAME 有权
标题翻译：用于传送测试托盘的侧锁式测试操作器和设备
公开(公告)号：US20090199395A1
公开(公告)日：2009-08-13
申请号：US12415662
申请日：2009-03-31
申请人： Jae Gyun Shim , Yun Sung Na , In Gu Jeon , Dong-Hyun Yo , Bong-Soo Kim , Choung-Min Joung
发明人： Jae Gyun Shim , Yun Sung Na , In Gu Jeon , Dong-Hyun Yo , Bong-Soo Kim , Choung-Min Joung
IPC分类号： B23P17/04 , B65G47/22 , H01L21/02 , B65G47/90 , H01L21/68 , H01L21/677
CPC分类号： G01R31/2893 , Y10T29/52
摘要： In a side-docking type test handler, a descending mechanism lowers a horizontally postured test tray, which has been transferred into a soak chamber, down to a descent finish position and a vertical posture changing mechanism changes the posture of the test tray, which has been lowered to the descent finish position, from the horizontal state to a vertical state, to transfer the test tray into a test chamber. Further, a horizontal posture changing mechanism changes the posture of the test tray in the test chamber from the vertical state to the horizontal state while transferring the test tray to an ascent start position in a desoak chamber.
摘要翻译：在侧对接式测试处理机中，下降机构降低已经被传送到浸泡室中的水平姿态的测试盘，直到下降完成位置，并且垂直姿势改变机构改变测试托盘的姿态，已经从水平状态下降到下降完成位置到垂直状态，以将测试托盘传送到测试室中。此外，水平姿势改变机构将测试盘中的测试托盘的姿势从垂直状态改变到水平状态，同时将测试托盘转移到脱泡室中的上升开始位置。

55. 发明申请

US20090035930A1 METHOD OF FORMING A WIRE STRUCTURE 有权
标题翻译：形成线结构的方法
公开(公告)号：US20090035930A1
公开(公告)日：2009-02-05
申请号：US12146729
申请日：2008-06-26
申请人： Ho-Jun Yi , Yong-ll Kim , Bong-Soo Kim , Dae-Young Jang , Woo-Jeong Cho
发明人： Ho-Jun Yi , Yong-ll Kim , Bong-Soo Kim , Dae-Young Jang , Woo-Jeong Cho
IPC分类号： H01L21/768
CPC分类号： H01L27/105 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence.
摘要翻译：在形成线结构的方法中，在衬底上形成第一有源区和第二有源区。每个第一有源区具有正斜率的第一侧壁和与第一侧壁相对的第二侧壁。第二有源区沿第一方向排列。隔离层位于第一有源区和第二有源区之间。第一掩模形成在第一有源区，第二有源区和隔离层上。第一掩模具有暴露第一侧壁并沿着第一方向延伸的开口。使用第一掩模蚀刻第一有源区，第二有源区和隔离层，以形成沿着第一方向延伸的凹槽，并形成具有高于凹槽的底面的高度的栅栏。形成线以填充凹槽。在导线上形成接触。接触件从栅栏朝向第二活动区域设置。

56. 发明授权

US07439581B2 Transistors, semiconductor integrated circuit interconnections and methods of forming the same 有权
公开(公告)号：US07439581B2
公开(公告)日：2008-10-21
申请号：US11704364
申请日：2007-02-09
申请人： Seong-Goo Kim , Kang-Yoon Lee , Yun-Gi Kim , Bong-Soo Kim
发明人： Seong-Goo Kim , Kang-Yoon Lee , Yun-Gi Kim , Bong-Soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L23/485 , H01L21/823437 , H01L21/823462 , H01L21/823475 , H01L29/42336 , H01L29/4236 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

57. 发明申请

US20080048333A1 Semiconductor Device Having Buried Word Line Interconnects and Method of Fabricating the Same 审中-公开
标题翻译：具有掩埋字线互连的半导体器件及其制造方法
公开(公告)号：US20080048333A1
公开(公告)日：2008-02-28
申请号：US11842416
申请日：2007-08-21
申请人： Hyeoung-Won Seo , Yun-Gi Kim , Young-Woong Son , Bong-Soo Kim
发明人： Hyeoung-Won Seo , Yun-Gi Kim , Young-Woong Son , Bong-Soo Kim
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L27/10891 , H01L21/743 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
摘要翻译：半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。栅极线设置在外围电路区域中的衬底上。字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分通过并与栅极线接触。

58. 发明申请

US20070284647A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070284647A1
公开(公告)日：2007-12-13
申请号：US11705109
申请日：2007-02-12
申请人： Hyeoung-Won Seo , Jae-Man Yoon , Kang-Yoon Lee , Bong-Soo Kim
发明人： Hyeoung-Won Seo , Jae-Man Yoon , Kang-Yoon Lee , Bong-Soo Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66628 , H01L27/10814 , H01L27/10876 , H01L27/10894 , H01L29/7834
摘要： A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
摘要翻译：半导体器件可以包括具有电池有源区的衬底。可以在电池活性区域中形成电池栅电极。单元栅极覆盖层可以形成在单元栅电极上。至少两个电池外延层可以形成在电池有源区上。至少两个单元外延层中的一个可以延伸到单元栅极覆盖层的一端，并且至少两个单元外延层中的另一个可以延伸到单元栅极覆盖层的相对端。电池杂质区域可以设置在电池活性区域中。电池杂质区域可以对应于至少两个电池外延层中的相应一个。

59. 发明授权

US06653225B2 Method for forming gate electrode structure with improved profile and gate electrode structure therefor 失效
公开(公告)号：US06653225B2
公开(公告)日：2003-11-25
申请号：US09970536
申请日：2001-10-03
申请人： Bong-Soo Kim , Byong-Sun Ju , Jae-Cheol Paik
发明人： Bong-Soo Kim , Byong-Sun Ju , Jae-Cheol Paik
IPC分类号： H01L214763
CPC分类号： H01L21/28061 , H01L21/28052 , H01L21/28123
摘要： A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal expansion by patterning a refractory metal silicide layer after performing a thermal process on a refractory metal silicide layer, thereby having a stable operation characteristic, and a method for manufacturing the same are provided.

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