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51. 发明申请

US20090002040A1 DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的DLL电路
公开(公告)号：US20090002040A1
公开(公告)日：2009-01-01
申请号：US11964824
申请日：2007-12-27
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.
摘要翻译：一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

52. 发明授权

US07948287B2 DLL circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的DLL电路
公开(公告)号：US07948287B2
公开(公告)日：2011-05-24
申请号：US11964824
申请日：2007-12-27
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.
摘要翻译：一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

53. 发明授权

US08514644B2 Bit line sense amplifier control circuit and semiconductor memory apparatus having the same 有权
标题翻译：位线读出放大器控制电路及其半导体存储装置
公开(公告)号：US08514644B2
公开(公告)日：2013-08-20
申请号：US12959590
申请日：2010-12-03
申请人： Hyung Soo Kim , Ki Myung Kyung , Ic Su Oh
发明人： Hyung Soo Kim , Ki Myung Kyung , Ic Su Oh
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/065 , G11C11/4091
摘要： A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal.
摘要翻译：位线读出放大器控制电路被配置为根据第一读出放大器使能信号和第二读出放大器使能信号来驱动位线读出放大器，其中位线读出放大器的驱动力响应列选择而改变控制信号。

54. 发明授权

US08810274B2 On-die termination circuit 有权
标题翻译：片上终端电路
公开(公告)号：US08810274B2
公开(公告)日：2014-08-19
申请号：US13657123
申请日：2012-10-22
申请人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K17/16
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

55. 发明授权

US08319520B2 On-die termination circuit 有权
标题翻译：片上终端电路
公开(公告)号：US08319520B2
公开(公告)日：2012-11-27
申请号：US13012972
申请日：2011-01-25
申请人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Hyung Soo Kim , Hae Rang Choi , Jae Min Jang
IPC分类号： H03K17/16
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

56. 发明授权

US08047454B2 Structure for fixing reducer for sprinkler in side wall 有权
标题翻译：侧壁喷淋头固定减速机结构
公开(公告)号：US08047454B2
公开(公告)日：2011-11-01
申请号：US12460554
申请日：2009-07-20
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： B05B15/10
CPC分类号： F16L3/18 , A62C31/28 , A62C35/68
摘要： The present invention relates to a structure for fixing a reducer for a sprinkler in a side wall, and more particularly, to a structure for fixing a reducer for a sprinkler for side wall construction, in which since the reducer can easily adjust a distance from the side wall in the horizontal direction, a connection work between the reducer and the sprinkler head for the side wall construction connected to the reducer can be conveniently performed.
摘要翻译：本发明涉及一种用于在侧壁中固定用于喷洒器的减速器的结构，更具体地，涉及用于固定用于侧壁结构的喷洒器的减速器的结构，其中由于减速器可以容易地调节距离侧壁在水平方向上，可以方便地进行与还原器连接的侧壁结构的减速器和喷头之间的连接作业。

57. 发明授权

US07843481B2 Light scanning device capable of producing non-coplanar scanning lines 有权
标题翻译：能够产生非共面扫描线的光扫描装置
公开(公告)号：US07843481B2
公开(公告)日：2010-11-30
申请号：US12252856
申请日：2008-10-16
申请人： Hyung Soo Kim , Sun Min Kin
发明人： Hyung Soo Kim , Sun Min Kin
IPC分类号： B41J15/14 , B41J27/00
CPC分类号： G03G15/326 , B41J2/473 , G03G15/0435 , H04N1/00525
摘要： An image forming apparatus having improved arrangement of photosensitive members and configuration of a light scanning device to enable size reduction is described. The image forming apparatus includes a plurality of photosensitive members, a light scanning device to irradiate light beams to the plurality of photosensitive members, so as to form electrostatic latent images on the photosensitive members, a plurality of developers to supply a developing agent to the photosensitive members, so as to form visible images on the photosensitive members, and a transfer drum disposed in contact with the photosensitive members and used to transfer the visible images such that the visible images overlap one another. Scanning lines, which are formed on the plurality of photosensitive members, respectively, by the light scanning device, are arranged in at least two different planes.
摘要翻译：描述了一种具有改进的感光构件布置的图像形成装置和光扫描装置的结构以使尺寸减小。图像形成装置包括多个感光构件，用于将光束照射到多个感光构件的光扫描装置，以便在感光构件上形成静电潜像，多个显影剂将显影剂供应到感光体以便在感光构件上形成可见图像，以及与感光构件接触设置的转印鼓，用于传送可见图像使得可视图像彼此重叠。分别由光扫描装置形成在多个感光构件上的扫描线被布置在至少两个不同的平面中。

58. 发明申请

US20080237407A1 Structure for fixing reducer for sprinkler in side wall 有权
公开(公告)号：US20080237407A1
公开(公告)日：2008-10-02
申请号：US11731693
申请日：2007-03-30
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： B05B3/02 , F16L3/08
CPC分类号： F16L3/18 , A62C31/28 , A62C35/68
摘要： Provided is a structure for fixing a reducer for a sprinkler in side wall construction, which includes a bracket, a reducer, and an adjusting bolt. The bracket includes a first transverse portion, a first longitudinal portion, a second transverse portion, and a second longitudinal portion. The first transverse portion includes an elongated hole formed in order to be fixed on a ceiling with at least one fixing member. The first longitudinal portion is bent perpendicularly with the first transverse portion at one end of the first transverse portion. The second transverse portion is formed in parallel with the first transverse portion on the bottom of the first longitudinal portion, in which a rail hole is formed in the plate surface thereof. The second longitudinal portion is formed in parallel with the first longitudinal portion at the end part of the second transverse portion, in which a screw tap is formed in the plate surface thereof and simultaneously a through-hole is formed in one side of the rail hole. The reducer includes a rail block and a plate. The rail block is formed into a linear type tubular body with one end of which a flexible tube is combined and with the other end of which the head of the sprinkler for side wall construction is combined. The rail block is arranged in parallel with the second transverse portion at the lower portion of the second transverse portion, and is protruded from the upper-center portion of the reducer, in which sliding grooves formed in the rail block are engaged with a rail hole formed at the second transverse portion to thereby allow the rail block to move in the form of a rail. The plate is arranged in parallel with the second longitudinal portion at the location spaced from the rail block, in which a through-hole is formed in the plate surface. The adjusting bolt is inserted into the through-hole of the plate and is screwed into a screw tap of the second longitudinal portion, to thus enable the reducer to reciprocate in the direction which is in parallel with the second transverse portion during forward and backward rotation. In this way, since the reducer is configured to easily adjust a distance from the side wall in the vertical direction as well as in the horizontal direction, a connection work between the reducer and the sprinkler head for the side wall construction connected to the reducer can be conveniently performed, and the intensity of the reducer fixing structure can be reinforced.

59. 发明授权

US09255652B2 Clamping structure for mounting reducer 有权
标题翻译：减速机用夹紧结构
公开(公告)号：US09255652B2
公开(公告)日：2016-02-09
申请号：US14100107
申请日：2013-12-09
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： F16L3/00 , F16L3/24 , F16L3/10
CPC分类号： F16L3/00 , F16B2/185 , F16L3/006 , F16L3/1075 , F16L3/24
摘要： Disclosed herein is a clamping structure for mounting a reducer. The clamping structure include a clamp body 431 that is formed at opposite sides thereof with a door connecting portion 431a and a latch member connecting portion 431b to form a rectangular shape with one open side, and a clamp door 434 that can be rotated about a hinge pin 433 formed at the door connecting portion 431a, wherein the clamp door 431 is formed at one side thereof with a fastening portion, to which a latch portion of a latch member 450 is latched to allow a lever handle 446 of a lever member 440 to be pushed, and wherein the lever member 440 is coupled at one end thereof to the latch member connecting portion 450 of the clamp body 431 by a hinge 444 and is rotatably coupled at a middle thereof to the latch member 450 by a hinge 454 of the latch member 450.
摘要翻译：这里公开了一种用于安装减速器的夹紧结构。夹紧结构包括：夹具主体431，其在其相对侧形成有门连接部分431a和闩锁构件连接部分431b，以形成具有一个开放侧面的矩形形状;以及夹具门434，其能够围绕铰链旋转销433形成在门连接部分431a处，其中夹具门431在其一侧形成有紧固部分，闩锁构件450的闩锁部分锁定到该紧固部分，以允许杆构件440的杠杆手柄446 并且其中杠杆构件440的一端通过铰链444联接到夹具主体431的闩锁构件连接部分450，并且通过铰链444的铰链454可旋转地联接到闩锁构件450的中间闩构件450。

60. 发明授权

US08867291B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08867291B2
公开(公告)日：2014-10-21
申请号：US13602140
申请日：2012-09-01
申请人： Hyung Soo Kim
发明人： Hyung Soo Kim
IPC分类号： G11C7/12 , G11C11/4094
CPC分类号： G11C7/12 , G11C11/4094
摘要： A semiconductor apparatus including an equalizing unit configured to equalize voltages of a bit line and a bit bar line in response to an equalization signal; a precharge circuit unit configured to supply a voltage to the bit line and the bit bar line in response to first and second precharge signals; and a control unit configured to receive the equalization signal, and generate the equalization signal as the first and second precharge signals according to a control signal.
摘要翻译：一种半导体装置，包括均衡单元，其被配置为响应于均衡信号来均衡位线和位线的电压; 预充电电路单元，被配置为响应于第一和第二预充电信号向位线和位线提供电压; 以及控制单元，被配置为接收均衡信号，并根据控制信号产生作为第一和第二预充电信号的均衡信号。

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