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51. 发明申请

US20100039142A1 INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
标题翻译：半导体器件的输入缓冲电路
公开(公告)号：US20100039142A1
公开(公告)日：2010-02-18
申请号：US12540496
申请日：2009-08-13
申请人： JI WANG LEE , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
发明人： JI WANG LEE , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
摘要翻译：半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

52. 发明申请

US20100039140A1 BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器的缓冲电路
公开(公告)号：US20100039140A1
公开(公告)日：2010-02-18
申请号：US12494757
申请日：2009-06-30
申请人： Ji Wang Lee , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
发明人： Ji Wang Lee , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.
摘要翻译：半导体存储装置的缓冲电路包括：缓冲部，被配置为通过将输入信号的电压电平与参考电压的电压电平进行比较来增大或减小输出节点的电压电平。当参考电压的电平低于目标电平时，电压补偿部分与输出节点成比例地与参考电压的变化成比例。

53. 发明申请

US20090231006A1 DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME 有权
标题翻译：占空比校正电路和半导体集成电路设备，包括它们
公开(公告)号：US20090231006A1
公开(公告)日：2009-09-17
申请号：US12331294
申请日：2008-12-09
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K5/151 , H03K2005/00058
摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
摘要翻译：占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发，延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

54. 发明申请

US20090146700A1 DUTY RATIO CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路
公开(公告)号：US20090146700A1
公开(公告)日：2009-06-11
申请号：US12178475
申请日：2008-07-23
申请人： Yong Ju Kim , Kun Woo Park , Kyung Hoon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Kun Woo Park , Kyung Hoon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03K5/1565 , H03L7/07
摘要： A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks.
摘要翻译：一种占空比校正电路，包括：参考时钟产生模块，被配置为产生与外部时钟的上升沿和下降沿同步并具有主要校正的占空比的第一和第二参考时钟;以及占空比调整块，用于产生第一和第二内部响应于第一和第二参考时钟的时钟，并且通过根据根据第一和第二参考时钟的第一和第二参考时钟之间的相位差产生的多个数字控制信号来调整第一和第二参考时钟的占空比，第二个内部时钟。

55. 发明授权

US07528631B2 Logic gate, scan driver and organic light emitting diode display using the same 有权
标题翻译：逻辑门，扫描驱动器和有机发光二极管显示使用相同
公开(公告)号：US07528631B2
公开(公告)日：2009-05-05
申请号：US11826321
申请日：2007-07-13
申请人： Bo Yong Chung , Wang Jo Lee , Hyung Soo Kim , Sang Moo Choi
发明人： Bo Yong Chung , Wang Jo Lee , Hyung Soo Kim , Sang Moo Choi
IPC分类号： H03K19/20
CPC分类号： H03K19/09441 , G09G3/3266 , G09G2310/06
摘要： A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.
摘要翻译：逻辑门包括用于接收输入信号的第一驱动器，以及与输入信号相对应地控制第一电源和第一节点之间的连接;耦合到第一节点和第二电源的第二驱动器，以及控制第一节点的电压，第三驱动器，用于根据第一节点的电压来控制输出端和第一电源之间的连接;控制晶体管，用于控制第三驱动器和第二电源之间的连接控制晶体管的栅电极和第二电源之间的连接的第四驱动器和控制晶体管的第一电极和控制晶体管的栅电极之间的第二电容器，其中晶体管是相同的的MOS晶体管。

56. 发明申请

US20090097608A1 PHASE DETECTING CIRCUIT AND CLOCK GENERATING APPARATUS INCLUDING THE SAME 有权
标题翻译：相位检测电路和时钟发生装置，包括它们
公开(公告)号：US20090097608A1
公开(公告)日：2009-04-16
申请号：US12026384
申请日：2008-02-05
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H03L7/089
摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.
摘要翻译：相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

57. 发明申请

US20090058476A1 RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：在半导体集成电路中使用的接收器电路
公开(公告)号：US20090058476A1
公开(公告)日：2009-03-05
申请号：US12171214
申请日：2008-07-10
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/00
CPC分类号： H04L7/0337
摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.
摘要翻译：一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度电压来控制读出放大器的驱动速度。

58. 发明申请

US20090041172A1 PHASE DETECTION CIRCUIT 有权
标题翻译：相位检测电路
公开(公告)号：US20090041172A1
公开(公告)日：2009-02-12
申请号：US12018770
申请日：2008-01-23
申请人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Yong Ju Kim , Kun Woo Park , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/085 , H03L7/091 , H03L7/10
摘要： A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values.
摘要翻译：相位检测电路包括：相位频率检测器，用于比较第一输入信号和第二输入信号，并输出第一相位比较信号和第二相位比较信号;以及感测电路，用于感测第一相位比较信号和第二相位比较信号，并输出具有不同逻辑值的相位检测信号。

59. 发明授权

US07485231B2 Activated sludge process using downflow sludge blanket filtration 有权
标题翻译：活性污泥法使用下流污泥毯过滤
公开(公告)号：US07485231B2
公开(公告)日：2009-02-03
申请号：US10927741
申请日：2004-08-27
申请人： Ik Tai Yeom , Hyung Soo Kim , Young Gyun Choi , Yong Hyo Park
发明人： Ik Tai Yeom , Hyung Soo Kim , Young Gyun Choi , Yong Hyo Park
IPC分类号： C02F3/00
CPC分类号： C02F3/12 , C02F1/24 , C02F3/308 , Y02W10/15
摘要： The present invention relates to an activated sludge process and apparatus for effectively removing organic matters, nutrient salts, particulates, etc. dissolved in sewage/waste water by operating activated sludge process of a high biomass concentration combined with a down-flow solid-liquid separation process utilizing a float-concentrated sludge blanket layer. The present invention provides a process for biologically treating sewage/waste water using activated sludge, comprising the steps of (a) floating a sludge by having micro bubbles rise to form a float-concentrated sludge blanket layer and (b) down-flowing mixed liquor, including activated sludge and solids, into the sludge blanket layer, thereby resulting in a solid-liquid separation and an apparatus for operating the process.
摘要翻译：本发明涉及一种活性污泥法和设备，用于通过操作具有高生物质浓度的活性污泥法与下流固 - 液分离相结合，有效除去溶解在污水/废水中的有机物，营养盐，微粒等使用浮法浓缩污泥层的方法。本发明提供一种使用活性污泥对污水/废水进行生物处理的方法，其特征在于，包括以下步骤：（a）通过使微气泡升高以形成浮渣浓缩污泥层，漂浮污泥;（b）向下流动的混合液，包括活性污泥和固体，进入污泥毯层，从而产生固液分离和用于操作该方法的装置。

60. 外观设计

USD585106S1 Tool for fixing reducer for sprinkler in side wall 有权
标题翻译：侧墙用喷头固定减速器工具
公开(公告)号：USD585106S1
公开(公告)日：2009-01-20
申请号：US29285506
申请日：2007-03-30
申请人： Hyung Soo Kim
设计人： Hyung Soo Kim

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