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51. 发明授权

US07683706B2 Gain amplifier having switched-capacitor structure for minimizing settling time 失效
标题翻译：具有开关电容器结构的增益放大器，用于最小化建立时间
公开(公告)号：US07683706B2
公开(公告)日：2010-03-23
申请号：US12195202
申请日：2008-08-20
申请人： Young Deuk Jeon , Young Kyun Cho , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
发明人： Young Deuk Jeon , Young Kyun Cho , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
IPC分类号： H03F1/02
CPC分类号： H03F3/005
摘要： Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.
摘要翻译：提供一种增益放大器，其具有能够最小化建立时间的开关电容器结构，其中输入电容器在第一时钟对输入信号进行采样期间连接到输入端子，因此放大器的输出端子预先复位到输入电容器的估计输出电压值而不是0。因此，放大器的输出端子的轻微移动足以在放大模式下稳定到期望值，从而可以减少回转时间，结果可以使整体建立时间和功耗最小化。

52. 发明申请

US20100052752A1 LOCK DETECTION CIRCUIT AND LOCK DETECTING METHOD 有权
标题翻译：锁定检测电路和锁定检测方法
公开(公告)号：US20100052752A1
公开(公告)日：2010-03-04
申请号：US12466283
申请日：2009-05-14
申请人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon
发明人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon
IPC分类号： H03L7/06
CPC分类号： H03L7/095
摘要： Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.
摘要翻译：提供锁定检测电路和锁定检测方法。锁定检测电路包括两个延迟器件，四个触发器和两个逻辑门，并且可以精确地检测锁相环（PLL）电路的锁定状态。因此，可以以简单的结构实现锁定检测电路，结果，锁定检测电路的尺寸可以小巧，并且可以消耗更少的电力。此外，锁定检测方法使锁定检测处理更简单，从而可以在短时间内检测锁定状态。

53. 发明申请

US20090091387A1 SWITCHED-CAPACITOR VARIABLE GAIN AMPLIFIER HAVING HIGH VOLTAGE GAIN LINEARITY 失效
标题翻译：具有高电压增益线性的开关电容器可变增益放大器
公开(公告)号：US20090091387A1
公开(公告)日：2009-04-09
申请号：US12195212
申请日：2008-08-20
申请人： Young Kyun CHO , Young Deuk Jeon , Jong Kee Kwon , Jong Dae Kim
发明人： Young Kyun CHO , Young Deuk Jeon , Jong Kee Kwon , Jong Dae Kim
IPC分类号： H03G3/30
CPC分类号： H03G1/0094 , H03F3/005 , H03F3/45475
摘要： Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.
摘要翻译：提供了具有高电压增益线性度的开关电容器可变增益放大器。根据上述放大器，采样电容器在采样相位和放大阶段被共享并使用，因此可以减小由电容器失配引起的电压增益误差。此外，使用单位电容阵列可以简化电路设计和布局。此外，在放大器中，根据需要，可以容易地将电压增益控制为大于或等于1，并且可以通过相对较大的反馈因子来降低功耗和kT / C噪声，从而增益放大性能可以要改进

54. 发明申请

US20080068237A1 MULTI-BIT PIPELINE ANALOG-TO-DIGITAL CONVERTER HAVING SHARED AMPLIFIER STRUCTURE 有权
标题翻译：具有共享放大器结构的多位管线模拟数字转换器
公开(公告)号：US20080068237A1
公开(公告)日：2008-03-20
申请号：US11695143
申请日：2007-04-02
申请人： Young Deuk Jeon , Seung Chul Lee , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
发明人： Young Deuk Jeon , Seung Chul Lee , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/168
摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure. The multi-bit pipeline ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected with an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein N is an integer greater than or equal to 1 and K is an integer greater than or equal to 2.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.
摘要翻译：提供了具有共享放大器结构的多位流水线模数转换器（ADC）。多位流水线ADC包括：采样和保持放大器（SHA），用于采样和保持输入模拟电压并消除输入电压的采样误差; 第一至第K级的N位闪存ADC接收模拟信号，将其转换为数字信号并输出数字信号; 第一到第K级的N位乘法数模转换器（MDAC）将从N位闪存ADC输出的数字信号与前级的输出信号之间的差值转换成模拟信号并输出模拟信号; 以及在第一时钟与第一级的N位MDAC的输出和第二时钟的SHA的输出连接的三级放大器，其中N是大于或等于1的整数，并且K是整数大于或等于2.在多位流水线ADC中，可以在消耗大量功率的SHA和第一级的MDAC之间共享放大器，从而可以降低功耗和芯片尺寸。

55. 发明授权

US6091289A Low pass filter 失效
标题翻译：低通滤波器
公开(公告)号：US6091289A
公开(公告)日：2000-07-18
申请号：US99388
申请日：1998-06-18
申请人： Won Chul Song , Jong Ryul Lee , Chang Jun Oh , Jong Kee Kwon , Ook Kim , Kyung Soo Kim
发明人： Won Chul Song , Jong Ryul Lee , Chang Jun Oh , Jong Kee Kwon , Ook Kim , Kyung Soo Kim
IPC分类号： H03H9/46 , H03H11/04 , H03K5/00
CPC分类号： H03H11/04
摘要： There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.
摘要翻译：公开了一种低频滤波器。低频截止滤波器包括滤波器电路，其具有连接在输入端子和输出端子之间的电容器和连接到具有非常大电阻的输出端子的有源电阻器，以及具有负反馈以设置偏置电压的偏置电路将所述有源电阻器设置为期望值，从而在半导体芯片内实现截止滤波器作为一组，其中电容器具有小电容。低通滤波器包括具有非常大电阻的有源电阻器，用于将有源电阻器的偏置电压设置为期望值的装置，以及连接在输出端子和地之间的电容器。因此，低通滤波器可以使用甚至小的电容器集成。

56. 发明授权

US08957661B2 DC-DC converter with modulation mode switch 有权
标题翻译：具有调制模式开关的DC-DC转换器
公开(公告)号：US08957661B2
公开(公告)日：2015-02-17
申请号：US13609670
申请日：2012-09-11
申请人： Sewan Heo , Yil Suk Yang , Jong Kee Kwon
发明人： Sewan Heo , Yil Suk Yang , Jong Kee Kwon
IPC分类号： G05F1/56 , H02M3/156 , H02M1/00
CPC分类号： H02M3/156 , H02M3/1563 , H02M2001/0006 , H02M2001/0035 , Y02B70/16
摘要： Disclosed is a DC-DC converter, including: a switch unit configured to generate output voltage for driving a load; an output voltage monitoring unit including a reference voltage generator generating reference voltage and a reference voltage capacitor maintaining the reference voltage when power of the reference voltage generator is interrupted and configured to generate a signal for setting the output voltage as the reference voltage; a switch controlling unit configured to control the switch unit by being operated in a pulse width modulation (PWM) mode or a pulse frequency modulation (PFM) mode by using the signal of the output voltage monitoring unit; and a mode determining and power interrupting unit configured to set an operating mode of the switch controlling unit as the PWM mode or the PFM mode according to a magnitude of the load and interrupt power of the reference voltage generator when operated in the PFM mode.
摘要翻译：公开了一种DC-DC转换器，包括：开关单元，被配置为产生用于驱动负载的输出电压; 输出电压监视单元，包括产生参考电压的参考电压发生器和在参考电压发生器的功率被中断时保持参考电压的参考电压电容器，并且被配置为产生用于设置输出电压作为参考电压的信号; 开关控制单元，其被配置为通过使用所述输出电压监视单元的信号以脉冲宽度调制（PWM）模式或脉冲频率调制（PFM）模式来操作所述开关单元; 以及模式确定和功率中断单元，被配置为在PFM模式下操作时，根据负载的大小和参考电压发生器的中断功率，将开关控制单元的工作模式设置为PWM模式或PFM模式。

57. 发明申请

US20130093407A1 DC-DC CONVERTER 有权
标题翻译： DC-DC转换器
公开(公告)号：US20130093407A1
公开(公告)日：2013-04-18
申请号：US13609670
申请日：2012-09-11
申请人： Sewan Heo , Yil Suk Yang , Jong Kee Kwon
发明人： Sewan Heo , Yil Suk Yang , Jong Kee Kwon
IPC分类号： G05F1/46
CPC分类号： H02M3/156 , H02M3/1563 , H02M2001/0006 , H02M2001/0035 , Y02B70/16
摘要： Disclosed is a DC-DC converter, including: a switch unit configured to generate output voltage for driving a load; an output voltage monitoring unit including a reference voltage generator generating reference voltage and a reference voltage capacitor maintaining the reference voltage when power of the reference voltage generator is interrupted and configured to generate a signal for setting the output voltage as the reference voltage; a switch controlling unit configured to control the switch unit by being operated in a pulse width modulation (PWM) mode or a pulse frequency modulation (PFM) mode by using the signal of the output voltage monitoring unit; and a mode determining and power interrupting unit configured to set an operating mode of the switch controlling unit as the PWM mode or the PFM mode according to a magnitude of the load and interrupt power of the reference voltage generator when operated in the PFM mode.
摘要翻译：公开了一种DC-DC转换器，包括：开关单元，被配置为产生用于驱动负载的输出电压; 输出电压监视单元，包括产生参考电压的参考电压发生器和在参考电压发生器的功率被中断时保持参考电压的参考电压电容器，并且被配置为产生用于设置输出电压作为参考电压的信号; 开关控制单元，被配置为通过使用所述输出电压监视单元的信号以脉冲宽度调制（PWM）模式或脉冲频率调制（PFM）模式来操作所述开关单元; 以及模式确定和功率中断单元，被配置为在PFM模式下操作时，根据负载的大小和参考电压发生器的中断功率，将开关控制单元的工作模式设置为PWM模式或PFM模式。

58. 发明授权

US08407276B2 Apparatus for calculating absolute difference 有权
标题翻译：用于计算绝对差的装置
公开(公告)号：US08407276B2
公开(公告)日：2013-03-26
申请号：US12843550
申请日：2010-07-26
申请人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F7/50
CPC分类号： G06F7/544
摘要： Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.
摘要翻译：提供了一种用于计算能够使用加法器有效地执行绝对差的绝对差的装置。用于计算绝对差的装置包括比较器，比较器比较两个整数的值，第一和第二选择器，每个选择器根据比较器的比较结果选择和输出两个整数中的一个;逆变器，补偿由第二选择器选择的结果值; 和加法器将由第一选择器选择的结果值相加，由逆变器补充的值，以及1。

59. 发明申请

US20120226831A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 审中-公开
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20120226831A1
公开(公告)日：2012-09-06
申请号：US13471236
申请日：2012-05-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

60. 发明授权

US07977979B2 High-speed multi-stage voltage comparator 失效
标题翻译：高速多级电压比较器
公开(公告)号：US07977979B2
公开(公告)日：2011-07-12
申请号：US12507357
申请日：2009-07-22
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03K5/22
CPC分类号： H03F3/45475 , H03F3/45968 , H03F2203/45212
摘要： A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).
摘要翻译：提供了一个高速多级电压比较器。多级电压比较器被配置为消除通过相应的偏移消除开关的前置放大器的输出的偏移，并且通过相应的复位开关复位前置放大器的输出以减少输出恢复时间。因此，多级电压比较器以高精度和高速运行，从而可以有效地应用于模数转换器（ADC），特别是高速逐次逼近寄存器ADC（SAR） ADC）。

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