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51. 发明授权

US08169026B2 Stress-induced CMOS device 有权
标题翻译：应力感应CMOS器件
公开(公告)号：US08169026B2
公开(公告)日：2012-05-01
申请号：US13242380
申请日：2011-09-23
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
摘要翻译：一种半导体器件，包括：二氧化硅层; n型场效应晶体管（NFET），其包括至少一个凹陷源极/漏极沟槽，并位于所述二氧化硅层的一部分上方; p型场效应晶体管（PFET），其包括至少一个凹陷源极/漏极沟槽并且位于所述二氧化硅层的一部分上方; 在NFET和PFET上的氮化物应力衬垫，氮化物应力衬垫填充NFET的至少一个凹陷源极/漏极沟槽和PFET的至少一个凹陷源极/漏极沟槽; 以及形成在所述二氧化硅层中的第一接触件，所述第一接触件邻接所述NFET或PFET之一。

52. 发明授权

US08105887B2 Inducing stress in CMOS device 有权
标题翻译：在CMOS器件中引起应力
公开(公告)号：US08105887B2
公开(公告)日：2012-01-31
申请号：US12500107
申请日：2009-07-09
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and forming a contact in the opening.
摘要翻译：本发明的第一方面提供一种形成半导体器件的方法，所述方法包括：提供互补金属氧化物半导体（CMOS）器件，其包括：硅衬底层; 二氧化硅层; 和具有第一凹陷源极/漏极沟槽的n型场效应晶体管（NFET）栅极和具有第二凹陷源极/漏极沟槽的p型场效应晶体管（PFET）栅极，所述NFET栅极和PFET栅极位于二氧化硅层; 在第一凹陷源极/漏极沟槽和第二凹陷源极/漏极沟槽中沉积氮化物应力衬垫; 在氮化物应力衬垫上沉积氧化物层; 将CMOS器件放置在处理晶片上，其中氧化物层最靠近处理晶片; 去除硅衬底层; 蚀刻所述二氧化硅层以形成邻接所述源/漏区的一部分的开口，所述源极/漏极区邻接所述第一凹陷源极/漏极沟槽或所述第二凹陷源极/漏极沟槽中的一个; 并在开口中形成接触。

53. 发明申请

US20120007190A1 STRESS-INDUCED CMOS DEVICE 有权
标题翻译：应力诱导CMOS器件
公开(公告)号：US20120007190A1
公开(公告)日：2012-01-12
申请号：US13242380
申请日：2011-09-23
申请人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , QingQing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/1203 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
摘要翻译：一种半导体器件，包括：二氧化硅层; n型场效应晶体管（NFET），其包括至少一个凹陷源极/漏极沟槽，并位于所述二氧化硅层的一部分上方; p型场效应晶体管（PFET），其包括至少一个凹陷源极/漏极沟槽并且位于所述二氧化硅层的一部分上方; 在NFET和PFET上的氮化物应力衬垫，氮化物应力衬垫填充NFET的至少一个凹陷源极/漏极沟槽和PFET的至少一个凹陷源极/漏极沟槽; 以及形成在所述二氧化硅层中的第一接触件，所述第一接触件邻接所述NFET或PFET之一。

54. 发明申请

US20110303951A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110303951A1
公开(公告)日：2011-12-15
申请号：US13060468
申请日：2010-09-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7834 , H01L29/045 , H01L29/105 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括半导体衬底; 半导体衬底上的第一半导体层; 围绕所述第一半导体层的第二半导体层; 形成在第一半导体层上的高k电介质层和栅极导体; 形成在第二半导体层中的源/漏区，其中第二半导体层具有与第一半导体层接触的倾斜侧壁。半导体器件具有增加的输出电流，增加的操作速度以及由于高移动性的沟道区域而导致的功率消耗降低。

55. 发明申请

US20110227170A1 MOSFET STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： MOSFET结构及其制造方法
公开(公告)号：US20110227170A1
公开(公告)日：2011-09-22
申请号：US12990714
申请日：2010-06-24
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： There is provided a MOSFET structure and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a dummy s gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.
摘要翻译：提供了一种MOSFET结构及其制造方法。该方法包括：提供半导体衬底; 在半导体衬底上形成虚拟栅极; 形成源/漏区; 选择性地将伪栅极蚀刻到要形成沟道的位置; 并且在通道的位置上外延生长通道层，并在通道层上形成栅极，其中沟道层包括高迁移率的材料。因此，在形成源极/漏极区域之后，器件的沟道被高迁移率的材料代替，因此可以抑制短沟道效应并且还能够提高器件性能。

56. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

57. 发明授权

US08981454B2 Non-volatile memory device using finfet and method for manufacturing the same 有权
标题翻译：使用finfet的非易失性存储器件及其制造方法
公开(公告)号：US08981454B2
公开(公告)日：2015-03-17
申请号：US13061461
申请日：2010-09-25
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/788 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/845 , H01L29/42324 , H01L29/785 , H01L29/7881
摘要： The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.
摘要翻译：本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。

58. 发明授权

US08928089B2 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08928089B2
公开(公告)日：2015-01-06
申请号：US13201827
申请日：2011-02-24
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate (100) with an nMOSFET region (102) and a pMOSFET region (104) on it. An nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region (102) and the pMOSFET region (104), respectively. The nMOSFET structure comprises a first channel region (182) formed in the nMOSFET region (102) and a first gate stack formed in the first channel region (182). The nMOSFET structure is covered with a compressive-stressed material layer (130) to apply a tensile stress to the first channel region (182). The pMOSFET structure comprises a second channel region (184) formed in the pMOSFET region (104) and a second gate stack formed in the second channel region (184). The pMOSFET structure is covered with a tensile-stressed material layer (140) to apply a compressive stress to the second channel region (184).
摘要翻译：提供半导体结构及其形成方法。该结构包括其上具有nMOSFET区域（102）和pMOSFET区域（104）的半导体衬底（100）。 nMOSFET结构和pMOSFET结构分别形成在nMOSFET区域（102）和pMOSFET区域（104）中。 nMOSFET结构包括形成在nMOSFET区域（102）中的第一沟道区（182）和形成在第一沟道区（182）中的第一栅叠层。 nMOSFET结构用压应力材料层（130）覆盖，以向第一沟道区域（182）施加拉伸应力。 pMOSFET结构包括形成在pMOSFET区域（104）中的第二沟道区（184）和形成在第二沟道区（184）中的第二栅叠层。 pMOSFET结构被拉伸应力材料层（140）覆盖，以向第二通道区域（184）施加压缩应力。

59. 发明授权

US08815698B2 Well region formation method and semiconductor base 有权
标题翻译：井区形成方法和半导体基础
公开(公告)号：US08815698B2
公开(公告)日：2014-08-26
申请号：US13381636
申请日：2011-07-26
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/04 , H01L21/76 , H01L21/8238 , H01L29/16 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L29/1608 , H01L29/161 , H01L29/66651
摘要： A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
摘要翻译：提供了半导体技术领域中的阱区形成方法和半导体基底。一种方法包括：在半导体衬底中形成隔离区以隔离有源区; 选择所述有源区域中的至少一个，以及在所选择的有源区域中形成第一阱区域; 形成掩模以覆盖所选择的有源区，并蚀刻其余的有源区，以便形成沟槽; 并通过外延生长半导体材料以填充凹槽。另一种方法包括：在半导体衬底中形成用于隔离有源区的隔离区; 在活跃区域形成井区; 蚀刻有源区以形成凹槽，使得凹槽具有小于或等于阱区深度的深度; 并通过外延生长半导体材料以填充凹槽。

60. 发明申请

US20140197410A1 Semiconductor Structure and Method for Manufacturing the Same 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140197410A1
公开(公告)日：2014-07-17
申请号：US13697096
申请日：2012-05-17
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/04
CPC分类号： H01L29/78 , H01L21/76283 , H01L29/04 , H01L29/66477 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78603 , H01L29/78618 , H01L29/78696
摘要： The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region. The stressed layer provides a favorable stress to the channel of the semiconductor device, thus facilitating improving the performance of the semiconductor device.
摘要翻译：本发明提供一种半导体结构的制造方法。该方法包括：提供SOI衬底并在所述SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层的沟槽，所述沟槽部分地进入BOX层; 形成填充所述沟槽的一部分的应力层; 形成覆盖沟槽中的应力层的半导体层。相应地，本发明还提供了通过上述方法形成的半导体结构。在根据本发明的半导体结构及其制造方法中，在超薄SOI衬底上形成沟槽，首先填充有应力层，然后填充半导体材料以准备形成源极/漏极地区。应力层对半导体器件的通道提供有利的应力，从而有助于提高半导体器件的性能。

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