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51. 发明申请

US20120191392A1 METHOD FOR ANALYZING CORRELATIONS AMONG DEVICE ELECTRICAL CHARACTERISTICS AND METHOD FOR OPTIMIZING DEVICE STRUCTURE 审中-公开
标题翻译：用于分析装置电气特性中的相关性的方法和用于优化装置结构的方法
公开(公告)号：US20120191392A1
公开(公告)日：2012-07-26
申请号：US13321684
申请日：2011-08-10
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： G06F19/00 , G01R27/00 , G01R19/00
CPC分类号： G06F17/5045 , G01R31/2846 , G06F2217/08 , H01L22/20
摘要： A method for analyzing correlations among electrical characteristics of an electronic device and a method for optimizing a structure of the electronic device are disclosed. The electronic device may comprises a plurality of electrical characteristics v1, v2, v3, . . . , vm, wherein the electrical characteristics v2, v3, . . . . , vm constitute a (m−1) dimensional space. For a plurality of discrete measurement points (v2k, v3k, . . . , vmk) in the (m−1) dimensional space, a plurality of corresponding measurement values of the electrical characteristic v1 has already been obtained. The method comprises: performing a Delaunay triangulation operation on the plurality of measurement points (v2k, v3k, . . . , vmk) in the (m−1) dimensional space; calculating a plurality of interpolation values of the electrical characteristic v1 corresponding to a plurality of interpolation points (v2i, v3i, . . . , vmi) by means of interpolation based on the result of the Delaunay triangulation operation; and determining the correlation between the electrical characteristics v1 and v2 from the plurality of measurement points and the plurality of interpolation points as well as the plurality of corresponding measurement values and the plurality of corresponding interpolation values.
摘要翻译：公开了一种用于分析电子设备的电特性之间的相关性的方法和用于优化电子设备的结构的方法。电子设备可以包括多个电气特征v1，v2，v3，...。。。，vm，其中电特性v2，v3，...，。。。，vm构成（m-1）维空间。对于（m-1）维空间中的多个离散测量点（v2k，v3k，...，vmk），已经获得了电特性v1的多个对应的测量值。该方法包括：对（m-1）维空间中的多个测量点（v2k，v3k，...，vmk）执行德劳内三角测量操作; 通过基于Delaunay三角测量运算结果的插值计算与多个插值点（v2i，v3i，...，vmi）对应的电特性v1的多个内插值; 以及确定来自所述多个测量点和所述多个内插点的电特性v1和v2之间的相关性以及所述多个对应的测量值和所述多个对应的内插值。

52. 发明申请

US20120112358A1 STACK-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：堆叠型半导体器件及其制造方法
公开(公告)号：US20120112358A1
公开(公告)日：2012-05-10
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

53. 发明申请

US20120091514A1 Semiconductor Junction Diode Device And Method For Manufacturing The Same 审中-公开
标题翻译：半导体结二极管器件及其制造方法
公开(公告)号：US20120091514A1
公开(公告)日：2012-04-19
申请号：US13377958
申请日：2011-02-27
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/8611 , H01L29/1602 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/6603 , H01L29/6606 , H01L29/6609 , H01L29/66128 , H01L29/66204 , H01L29/861
摘要： A semiconductor junction diode device structure and a method for manufacturing the same are provided, where a gate of the diode device structure is directly formed on the substrate, a P-N junction is formed in the semiconductor substrate, a first contact is formed on the gate, and a second contact is formed on the doped region at both sides of the gate, the first contact and the second contact acting as cathode/anode of the diode device, respectively. The diode device of this structure occupies a small area, and its forming process may be integrated in a gate-last integration process of MOSFET devices, which needs no additional mask and costs and has a high integration level.
摘要翻译：提供一种半导体结二极管器件结构及其制造方法，其中二极管器件结构的栅极直接形成在衬底上，在该半导体衬底中形成PN结，在栅极上形成第一接触，并且第二接触形成在栅极两侧的掺杂区域上，第一接触和第二接触分别用作二极管器件的阴极/阳极。该结构的二极管器件占地面积小，其形成过程可集成在MOSFET器件的最终集成过程中，无需额外的掩模和成本，并具有较高的集成度。

54. 发明授权

US09653358B2 Semiconductor device structure and method for manufacturing the same 有权
公开(公告)号：US09653358B2
公开(公告)日：2017-05-16
申请号：US13133061
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/02 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/823814 , H01L21/823828 , H01L21/823878 , H01L27/0207 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/66575 , H01L29/66651 , H01L29/78 , H01L29/7848
摘要： The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.

55. 发明授权

US08460988B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08460988B2
公开(公告)日：2013-06-11
申请号：US13061824
申请日：2010-09-26
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/3086 , H01L21/76897 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7843 , H01L29/7848
摘要： A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.
摘要翻译：提供一种制造半导体器件的方法，其中在形成栅极堆叠及其第一间隔物之后，形成第二间隔物和第三间隔物; 然后通过移除第二间隔件在第一间隔件和第三间隔件之间形成开口。通过在第一间隔件208和第三间隔件212之间形成开口214来限制凸起的有效区域220的形成范围。凸起的有源区域220以自对准的方式形成在开口214中，使得可以实现凸起的有效区域220的更好的轮廓，并且可以避免由无限制的方式引起的相邻设备之间的可能的短路。此外，基于这样的制造方法，可以容易地利用凸起的有源区域220冲洗栅电极204，并且也容易实施双应力氮化物工艺，以增加器件的移动性。

56. 发明申请

US20120223398A1 METHOD FOR MANUFACTURING CONTACT AND SEMICONDUCTOR DEVICE HAVING SAID CONTACT 有权
标题翻译：制造接触器的方法和具有接触的半导体器件
公开(公告)号：US20120223398A1
公开(公告)日：2012-09-06
申请号：US13144887
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76877 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a method for manufacturing a contact and a semiconductor device having said contact. The present invention proposes to form first a trench contract of relatively large size, then to form one or more dielectric layer(s) within the trench contact, and then to remove the upper part of the dielectric layer(s) and to fill the same with a conductive material. The use of such a method makes it easy to form a trench contact of relatively large size which is easy for manufacturing; besides, since dielectric layer(s) is/are formed in the trench contact, thence capacitance between a source/drain trench contact and a gate electrode is reduced accordingly.
摘要翻译：本发明涉及一种用于制造接触的方法和具有所述接触的半导体器件。本发明提出首先形成相对大尺寸的沟槽接合，然后在沟槽接触中形成一个或多个电介质层，然后去除电介质层的上部并填充相同的电介质层与导电材料。使用这种方法可以容易地形成容易制造的较大尺寸的沟槽接触; 此外，由于在沟槽接触中形成介电层，所以源极/漏极沟槽接触和栅电极之间的电容相应地减小。

57. 发明申请

US20120187497A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120187497A1
公开(公告)日：2012-07-26
申请号：US13380975
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823475 , H01L27/092 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.
摘要翻译：本发明提出一种半导体器件结构及其制造方法，涉及半导体制造业。该方法包括：提供半导体衬底; 在半导体衬底上形成栅电极线; 在栅电极线的两侧形成侧壁间隔物; 在栅极电极线的两侧在半导体基板上形成源极/漏极区域; 在栅电极线或源极/漏极区上形成接触孔; 并且在形成侧壁间隔物之后但在用于半导体器件结构的FEOL处理完成之前，切断栅电极线以形成电隔离的栅电极。本发明的实施例可用于制造集成电路。

58. 发明申请

US20120132923A1 SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME 有权
标题翻译：用于集成电路的基板及其形成方法
公开(公告)号：US20120132923A1
公开(公告)日：2012-05-31
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/161 , H01L29/20 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

59. 发明申请

US20120126245A1 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：浅层分离结构及其形成方法
公开(公告)号：US20120126245A1
公开(公告)日：2012-05-24
申请号：US13132068
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/762 , H01L29/12 , H01L29/06 , H01L29/16 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/76232
摘要： The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其形成方法。 STI结构包括半导体衬底; 第一沟槽，其嵌入在所述半导体衬底中并填充有第一介电层; 以及形成在所述半导体衬底的顶表面上并与所述第一沟槽互连的第二沟槽，其中所述第二沟槽填充有第二介电层，所述第二介电层的顶表面与所述半导体衬底的顶表面冲洗，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减小了图形的尺寸并提高了半导体器件的性能。

60. 发明申请

US20120025317A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120025317A1
公开(公告)日：2012-02-02
申请号：US13003969
申请日：2010-09-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L29/66545 , H01L29/78
摘要： A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.
摘要翻译：一种半导体器件结构及其制造方法。一种制造半导体器件结构的方法包括在半导体衬底上形成栅极线; 形成围绕所述栅极线的栅极侧壁间隔物; 在半导体衬底中和各个栅极线的任一侧上形成相应的源/漏区; 形成围绕所述栅极侧壁间隔物的导电侧壁间隔物并且在切割栅极线是电隔离栅极的预定位置处切断栅极线，栅极侧壁间隔物和导电侧壁间隔物，并且切割的导电侧壁间隔物是电隔离的下部触点。该方法适用于集成电路中触点的制造。

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