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    • 51. 发明申请
    • OUTPUT METHOD FOR IMPROVING VIDEO IMAGE QUALITY
    • 用于改善视频图像质量的输出方法
    • US20060078045A1
    • 2006-04-13
    • US10907441
    • 2005-04-01
    • Ying-Chih YangTsung-Hsien LinJen-Yi Liao
    • Ying-Chih YangTsung-Hsien LinJen-Yi Liao
    • H04N7/12
    • H04N5/21H04N5/4401H04N19/117H04N19/159H04N19/172H04N19/44H04N19/61H04N21/440218H04N21/4621
    • An output method for improving video image quality is provided. First, a frame data of a first frame is received, wherein the first frame may coincide with a first type or a second type. Thereafter, the first frame is subjected to a signal process step to output a processed first frame with a first standard, wherein the processed first frame comprises a first signal to noise (S/N) ratio. Next, a frame data of a second frame with a second standard is received, wherein the second frame coincides with a third type. Thereafter, a first decompression process of frame data is performed on the second frame to output a processed second frame with the first standard, wherein the processed second frame comprises a second S/N ratio. In addition, a difference between the first S/N ratio and the second S/N ratio is smaller than a predetermined minimum tolerance.
    • 提供了一种用于提高视频图像质量的输出方法。 首先,接收第一帧的帧数据,其中第一帧可以与第一类型或第二类型重合。 此后,对第一帧进行信号处理步骤以输出具有第一标准的经处理的第一帧,其中处理的第一帧包括第一信噪比(S / N)比。 接下来,接收具有第二标准的第二帧的帧数据,其中第二帧与第三类型重合。 此后,对第二帧执行帧数据的第一解压缩处理,以输出具有第一标准的经处理的第二帧,其中处理后的第二帧包括第二S / N比。 此外,第一S / N比和第二S / N比之间的差小于预定的最小容差。
    • 52. 发明授权
    • High speed differential signaling logic gate and applications thereof
    • 高速差分信号逻辑门及其应用
    • US06998877B2
    • 2006-02-14
    • US10842608
    • 2004-05-10
    • Tsung-Hsien Lin
    • Tsung-Hsien Lin
    • H03K19/20
    • H03K19/09432
    • A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output. The 2nd load is coupled to the drain of the complimentary transistor to provide a 2nd phase of the differential logic output.
    • 一个高速差分信号逻辑门包括一个输入晶体管,第二输入晶体管,互补晶体管,电流源,第一输入晶体管,第二输入晶体管, 负载和2 负载。 第一输入晶体管可操作地耦合以接收第一差分输入信号的第一输入逻辑信号,其可以是第一差分输入信号的一相。 第二输入晶体管与第一输入晶体管并联耦合,并进一步耦合以接收第二输入逻辑信号,其中, 可以是差分输入信号的2相。 互补晶体管可操作地耦合到第一和第二和第二输入晶体管的源极并且接收互补输入信号,其模拟1 相位差分逻辑输出。 二极管负载耦合到互补晶体管的漏极以提供差分逻辑输出的第二相。
    • 53. 发明授权
    • 50% duty-cycle clock generator
    • 50%占空比时钟发生器
    • US06990143B2
    • 2006-01-24
    • US10132856
    • 2002-04-25
    • Tsung-Hsien Lin
    • Tsung-Hsien Lin
    • H04B17/00H04B3/46H04Q1/20
    • H03K5/1565H03L7/0812
    • A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.
    • 一种用于从参考时钟产生五十%占空比时钟的方法和装置。 该方法和装置包括边缘发生器,可控延迟模块,占空比控制环模块和复位电路。 边缘发生器被耦合以产生参考时钟的干净边缘。 可控延迟模块被耦合以基于占空比控制信号从干净边缘产生延迟边缘。 占空比控制环模块被耦合以基于延迟边沿和参考时钟信号产生占空比控制信号。 复位电路被耦合以复位边缘发生器以产生第二边缘。 第二边缘被可控延迟模块延迟以产生第二延迟边缘,使得延迟边缘和第二延迟边缘构成百分之五十占空比时钟的一个周期。
    • 54. 发明授权
    • Divider module for use in an oscillation synthesizer
    • 用于振荡合成器的分频模块
    • US06980789B2
    • 2005-12-27
    • US10958916
    • 2004-10-05
    • Tsung-Hsien Lin
    • Tsung-Hsien Lin
    • H03K17/041H03K23/66H03L7/18H03L7/197H03K3/289
    • H03L7/18H03K17/04106H03K23/667H03L7/1976
    • A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.
    • 用于振荡合成器的分频器模块包括多个触发器和逻辑电路。 多个触发器可互操作地耦合以产生基于控制信号的分频值。 逻辑电路可操作地耦合以基于分频器选择信号产生控制信号。 多个触发器中的每一个包括第一差分锁存模块,第二差分锁存模块。 第一差分锁存模块可操作地耦合以产生基于差分触发器输入信号的差分锁存信号。 第二差分锁存模块可操作地耦合以产生基于差分锁存信号的差分触发器输出。 第一和第二差分锁存模块中的每一个包括采样晶体管部分,保持晶体管部分,第一选通电路和第二门控电路。
    • 55. 发明授权
    • Applications of a differential latch
    • 差分锁存器的应用
    • US06819915B2
    • 2004-11-16
    • US10728201
    • 2003-12-04
    • Tsung-Hsien Lin
    • Tsung-Hsien Lin
    • H04B138
    • H03K3/356139H03K3/0375H03K23/667
    • A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.
    • 差分锁存器包括采样晶体管部分,保持晶体管部分,第1门控电路和第2门控电路。 当与电源电压(例如,VDD和VSS)耦合到差分输入信号时,采样晶体管部分可操作地耦合到采样。 当耦合到电源电压时,保持晶体管部分可操作地耦合到锁存器,以产生锁存的差分信号。 第一门控电路可操作以根据时钟逻辑运算和第二时钟逻辑运算将采样的晶体管部分耦合到电源电压。 第二门控电路可操作以根据3时钟逻辑运算和4时钟逻辑运算将保持晶体管部分耦合到电源电压。
    • 59. 发明申请
    • Resin Composition, and Prepreg and Printed Circuit Board Prepared Using the Same
    • 树脂组合物,以及使用其制备的预浸料和印刷电路板
    • US20120097437A1
    • 2012-04-26
    • US13006530
    • 2011-01-14
    • Shih-Hao LiaoChih-Wei LiaoHsuan-Hao HsuHsien-Te ChenTsung-Hsien Lin
    • Shih-Hao LiaoChih-Wei LiaoHsuan-Hao HsuHsien-Te ChenTsung-Hsien Lin
    • H05K1/03C08K3/34C08L63/00
    • H05K1/0373C08G59/4014C08L63/00H05K1/0366H05K3/022
    • A resin composition is provided. The resin composition comprises: an epoxy resin; a polymer solution as a hardener, which is prepared by the following steps: (a) dissolving an N,O-heterocyclic compound into a first solvent to form a first reaction solution, wherein the N,O-heterocyclic compound is of Formula I or Formula II: wherein, R1 to R3, W1, W2, m, n, p and q are defined in the specification; (b) heating the first reaction solution to a first temperature to carry out a ring-opening polymerization; and (c) cooling the first reaction solution to a second temperature to substantially terminate the ring-opening polymerization, and thus obtain the polymer solution, wherein, the first solvent is unreactive to the N,O-heterocyclic compound; the first temperature is higher than the softening temperature of the N,O-heterocyclic compound and lower than the boiling point of the first solvent; and the second temperature is lower than the first temperature, and wherein, the amount of the hardener, based on the solid, is about 20 parts by weight to about 200 parts by weight per 100 parts by weight of the epoxy resin.
    • 提供树脂组合物。 树脂组合物包含:环氧树脂; 作为硬化剂的聚合物溶液,其通过以下步骤制备:(a)将N,O-杂环化合物溶解在第一溶剂中以形成第一反应溶液,其中所述N,O-杂环化合物为式I或 式II:其中,R1至R3,W1,W2,m,n,p和q在说明书中定义; (b)将第一反应溶液加热至第一温度以进行开环聚合; 和(c)将第一反应溶液冷却至第二温度以基本上终止开环聚合,从而获得聚合物溶液,其中第一溶剂对N,O-杂环化合物不反应; 第一温度高于N,O-杂环化合物的软化温度,低于第一溶剂的沸点; 并且第二温度低于第一温度,并且其中,基于固体的固化剂的量为每100重量份环氧树脂约20重量份至约200重量份。