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51. 发明专利

JPS5539606A REFERENCE VOLTAGE GENERATION DEVICE 失效
公开(公告)号：JPS5539606A
公开(公告)日：1980-03-19
申请号：JP11171878
申请日：1978-09-13
申请人： HITACHI LTD
发明人： MEGURO RIYOU , NAGASAWA KOUICHI , YAMASHIRO OSAMU , YOU KANJI
IPC分类号： H03F3/345 , H01L21/822 , H01L27/04 , H01L27/088 , H01L29/78 , H03F3/34 , H03K3/0233 , H03K19/003 , H03K19/0185
摘要： PURPOSE:To obtain reference voltage with few variations and no need of adjustment after manufacturing by taking out the voltage equal to the difference between Fermi levels of Al and P-type or intrinsic Si as the reference voltage. CONSTITUTION:Difference in Fermi levels of 1.15eV between P Si and Al and of 0.60eV between intrinsic Si and Al are little dependent on temperature and suitable for a reference voltage generation device. Intrinsic polycrystal Si 4 is stacked on a gate oxidation film of N-type Si 1 and a SiO2 mask 6 is provided. After making openings selectively, a P-layer 8 and a P-type polycrystal Si film 7 are formed. With coating of PSG 9 and openings made selectively thereupon, heat treatment is effected with the provision of Al electrodes 11 and 12 to alloy Al with polycrystal Si in holes 10. At this stage, thershold voltages for IGFETA-C are given by -0.8V, -1.4V and -1.95V respectively and these values are almost equal to the difference in Ferimi levels of Al and Si at the central portion of the gate electrode. With this arrangement, after connecting drains and gates for FETT1, T2 in common, thus obtained device is operated with a constant-current supply I0 and then the difference in thershold voltages is taken out from the difference in drain voltages as the reference.

52. 发明专利

JPS5539413A SCHMITT TRIGGER CIRCUIT 失效
公开(公告)号：JPS5539413A
公开(公告)日：1980-03-19
申请号：JP11172578
申请日：1978-09-13
申请人： HITACHI LTD
发明人： YOU KANJI , YAMASHIRO OSAMU
IPC分类号： H03K3/354 , H01L21/822 , H01L27/04 , H03F3/45 , H03K3/0233 , H03K3/353 , H03K3/3565 , H03K19/003 , H03K19/0185
摘要： PURPOSE:To obtain a Schmitt trigger circuit which is affected less by the change of the ambient conditions such as the power voltage and the like as well as the dispersion of the using MISFET's. CONSTITUTION:The Schmitt trigger circuit consists of inverter 1 to which input signal Vi is applied, inverter 2 which uses the output of inveter 1 as its input to form output Vo and MISFETT3 which is provided between the earth and the input terminal of inverter 2 to be controlled by output Vo. In such constitution, a selection is given to the threshold voltage of one side (T2) among the MISFET's forming inverter 1 of the first step with a higher amount equivalent to the voltage based on the Fermi level difference than the threshold voltage of the MOSFET featuring the same conducting channel of the other side. As a result, nearly a constant width of the hysteresis curve can be secured for the circuit irrespective of the change of various ambient conditions or the dispersion of the using MISFET's.

53. 发明专利

JPS5539412A INSULATING GATE FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效
公开(公告)号：JPS5539412A
公开(公告)日：1980-03-19
申请号：JP11172478
申请日：1978-09-13
申请人： HITACHI LTD
发明人： YAMASHIRO OSAMU , YOU KANJI , NISHIMURA KOUTAROU , NARITA KAZUTAKA
IPC分类号： H03F3/345 , H01L21/822 , H01L27/04 , H01L29/78 , H03F3/34 , H03F3/347 , H03K3/0233 , H03K19/003 , H03K19/0185
摘要： PURPOSE:To obtain a reference voltage generator which is formed into an integrated circuit in a high accuracy. CONSTITUTION:Heat oxide film 102 is formed on the surface of semiconductor substrate 101, and then etched at the area where the MISFET is formed to form gate oxide film 103. Then film 103 is etched selectively at the area having a contact to the poly Si-layer to form contact hole 103a. The Si is deposited through the CVD method on the entire main surface of substrate 101 to form polycrystal Si-layer 104 for the selective etching. Thus the SiO2 film is formed on the entire main surface of substrate 101 through the CVD method, and SiO2 film 105 is left behind selectively only on the poly-crystal Si-layer at the high resistance part and instrinsic level gate part 104a. Then the phosphorus is diffused within substrate 101 to form gata electrode 104b, contact part 104c and poly-crystal Si wiring part 104d each. And both the PSG film and the Al film are formed on the entire surface of substrate 101, and then the Al film is etched selectively to form the wiring region. Thus the desired device can be obtained.

54. 发明专利

JPS54119653A CONSTANT VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPS54119653A
公开(公告)日：1979-09-17
申请号：JP2544478
申请日：1978-03-08
申请人： HITACHI LTD
发明人： YOU KANJI , YAMASHIRO OSAMU
IPC分类号： G05F3/24 , G05F1/56
摘要： PURPOSE:To produce a high-accuracy constant voltage which has little scatter and is hardly affected by temperature, by providing two insulator-gate field-effect semiconductor devices different in electric characteristics. CONSTITUTION:An element for picking out the energy gap of silicon as a voltage signal has P -type semiconductor regions 4, 5 constituting the sources and drains of MIS FET's on an n-type semiconductor substrate 1. A semiconductor impurity of the same electroconductive type as the substrate is contained in a polysilicon layer constituting the gate 6' of one MIS FET Q1. A semiconductor impurity of the opposite electroconductive type to the substrate is contained in a polysilicon layer constituting the gate 6 of another MIS FET Q2. The drain and gate of the MIS FET Q1 of lower work function are connected to each other to supply a power voltage through a load resistor R1. Thus, a constant voltage generating circuit having a high accuracy and appropriate as a monolithic integrated circuit is obtained.

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