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51. 发明专利

JPS5931052A Semiconductor ic device and manufacture thereof 失效
标题翻译：半导体IC器件及其制造
公开(公告)号：JPS5931052A
公开(公告)日：1984-02-18
申请号：JP13993282
申请日：1982-08-13
申请人： Hitachi Ltd
发明人： YASUOKA HIDEKI , TANIZAKI YASUNOBU , MURAMATSU AKIRA , ANZAI NORIO
IPC分类号： H01L29/78 , H01L21/76 , H01L21/8249 , H01L27/00 , H01L27/06 , H01L27/092
CPC分类号： H01L21/76 , H01L21/8249 , H01L27/0623 , H01L27/092
摘要： PURPOSE: To make a circuit highly integrated by a method wherein the poly Si gate technology and the oxide film separating technology utilized for bypolar IC are combined with each other.
CONSTITUTION: An n
+ type embedded layer 3, an n
- type Si layer 2 are formed on a high resistance p
- type Si substrate 1. Firstly a p type diffused layer 5 and an n
+ type diffused layer 6 are formed. Secondly a p
- type well 7 is formed simultaneously connecting the layer 5 to the substrate 1 to separate the regions. Thirdly a field oxide film 10, a p type diffused layer 12 and a gate oxide film 13 are formed. Fourthly Si is deposited on the overall surface to form a poly Si gate 14. Fifthly CVD.oxide film 15 is deposited to form a p
+ source.drain film 16. In the final stage, an insulating film 20 and an Al electrode 21 are formed.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过将多晶硅栅极技术和用于极性IC的氧化膜分离技术彼此组合的方法使电路高度集成。构成：在高电阻p型Si衬底1上形成n +型嵌入层3，n +型Si层2.首先，将ap型扩散层5和n +型扩散形成层6。其次，同时将层5与基板1连接以形成区域，形成p型阱7。第三，形成场氧化膜10，p型扩散层12和栅极氧化膜13。第四，将Si沉积在整个表面上以形成多晶硅栅极14.第五，沉积CVD氧化物膜15以形成ap +源极导电膜16.在最后阶段，绝缘膜20和Al电极21 形成。

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