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51. 发明授权

US07428689B2 Data memory system and method for transferring data into a data memory 有权
标题翻译：用于将数据传送到数据存储器的数据存储器系统和方法
公开(公告)号：US07428689B2
公开(公告)日：2008-09-23
申请号：US11217081
申请日：2005-08-30
申请人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
发明人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
IPC分类号： G06F11/10
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译：提出了一种使用数据协议将数据传输到数据存储器中的方法。数据存储器是纠错码（ECC）存储器或非纠错码存储器。数据协议具有不同的帧。当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

52. 发明申请

US20080198676A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH A CHANGEABLE SUBSTRATE POTENTIAL 有权
标题翻译：具有可变基底电位的半导体存储器件和方法
公开(公告)号：US20080198676A1
公开(公告)日：2008-08-21
申请号：US12032336
申请日：2008-02-15
申请人： Marcel Berthel , Axel Strobel , Dominique Savignac , Helmut Schneider
发明人： Marcel Berthel , Axel Strobel , Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/06
CPC分类号： G11C11/4074 , G11C5/146 , G11C7/06 , G11C7/065 , G11C7/08 , G11C8/18 , G11C11/4091
摘要： A semiconductor memory device and method with a changeable substrate potential. One embodiment provides for operating a semiconductor memory device having at least one read or write/sense amplifier. The method includes changing the substrate potential of the read or write/sense amplifier.
摘要翻译：具有可变衬底电位的半导体存储器件和方法。一个实施例提供了用于操作具有至少一个读/写/读放大器的半导体存储器件。该方法包括改变读/写/读出放大器的衬底电位。

53. 发明申请

US20080002515A1 MEMORY WITH ALTERABLE COLUMN SELECTION TIME 审中-公开
标题翻译：具有可选列选择时间的记忆
公开(公告)号：US20080002515A1
公开(公告)日：2008-01-03
申请号：US11768160
申请日：2007-06-25
申请人： Helmut Schneider , Dominique Savignac
发明人： Helmut Schneider , Dominique Savignac
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4087 , G11C2207/002
摘要： A memory contains memory cells and is clock-controlled on the basis of a basic clock signal at the frequency fc, wherein a chosen memory cell is accessed by closing an addressed column selection switch. The memory has a pulse generator to produce a column selection pulse which closes the addressed column selection switch, wherein the pulse generator contains a first pulse timer for prescribing a fixed time Tf for the length Txof the column selection pulse and a second pulse timer for prescribing a frequency-dependent time Tv, which is proportional to the clock signal period Tc=1/fc, for the length of the column selection pulse.
摘要翻译：存储器包含存储器单元，并且基于频率为f C c C c的基本时钟信号进行时钟控制，其中通过关闭寻址列选择开关来访问所选存储单元。存储器具有脉冲发生器以产生列选择脉冲，其闭合寻址列选择开关，其中脉冲发生器包含第一脉冲定时器，用于为长度T SUB定义固定时间T < x 和第二脉冲计时器，用于规定与时钟信号周期T T = 0成正比的频率相关时间T < 对于列选择脉冲的长度，1 / f C 。

54. 发明申请

US20070153601A1 INTEGRATED CIRCUIT AND METHOD OF OPERATING SUCH A CIRCUIT 失效
标题翻译：集成电路和操作这种电路的方法
公开(公告)号：US20070153601A1
公开(公告)日：2007-07-05
申请号：US11566553
申请日：2006-12-04
申请人： Dominique Savignac , Helmut Schneider
发明人： Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/065 , G11C11/4091 , G11C2207/065
摘要： An integrated circuit comprises a bit line pair having two bit lines, a sense amplifier having at least one transistor, the sense amplifier amplifying a charge difference between the bit lines of the bit line pair; and a control unit connected to a substrate terminal of the at least one transistor, the control unit applying a substrate potential dependent on an operating state of the integrated circuit to the substrate of the at least one transistor.
摘要翻译：集成电路包括具有两个位线的位线对，具有至少一个晶体管的读出放大器，所述读出放大器放大位线对的位线之间的电荷差; 以及连接到所述至少一个晶体管的衬底端子的控制单元，所述控制单元将所述集成电路的操作状态的衬底电位施加到所述至少一个晶体管的衬底。

55. 发明申请

US20070023898A1 Integrated circuit chip and integrated device 失效
标题翻译：集成电路芯片和集成器件
公开(公告)号：US20070023898A1
公开(公告)日：2007-02-01
申请号：US11192663
申请日：2005-07-29
申请人： Minka Gospodinova , Jochen Thomas , Dominique Savignac
发明人： Minka Gospodinova , Jochen Thomas , Dominique Savignac
IPC分类号： H01L23/48
CPC分类号： H01L23/66 , H01L23/13 , H01L23/49822 , H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/4824 , H01L2224/49052 , H01L2224/49109 , H01L2224/49174 , H01L2224/4943 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00
摘要： Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are intelligently arranged to reduce the loop inductance of corresponding signal and power supply bond wires.
摘要翻译：实施例提供了具有这种集成电路的集成电路芯片和器件，其中不同类型的焊盘以单独的行布置。在一个实施例中，焊盘被智能地布置成减小对应的信号和电源接合线的环路电感。

56. 发明授权

US07072233B2 Method and apparatus for optimizing the functioning of DRAM memory elements 失效
标题翻译：用于优化DRAM存储器元件的功能的方法和装置
公开(公告)号：US07072233B2
公开(公告)日：2006-07-04
申请号：US10850817
申请日：2004-05-21
申请人： Ruediger Brede , Dominique Savignac , Helmut Fischer
发明人： Ruediger Brede , Dominique Savignac , Helmut Fischer
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/028 , G11C7/1045 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C29/50012
摘要： In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.
摘要翻译：在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作，首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间正常运行模式。

57. 发明申请

US20050002245A1 Method and apparatus for optimizing the functioning of DRAM memory elements 失效
标题翻译：用于优化DRAM存储器元件的功能的方法和装置
公开(公告)号：US20050002245A1
公开(公告)日：2005-01-06
申请号：US10850817
申请日：2004-05-21
申请人： Ruediger Brede , Dominique Savignac , Helmut Fischer
发明人： Ruediger Brede , Dominique Savignac , Helmut Fischer
IPC分类号： G11C7/10 , G11C11/4076 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C7/1045 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C29/50012
摘要： In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration. Then information on the modified default time duration or on the ascertained real time duration are stored in the memory element during the test operation mode, wherein the second operation is executed offset by the modified default time duration after the execution instant of the first operation during the normal operation mode.
摘要翻译：在用于修改第二操作的执行时刻和先前在存储元件中执行的第一操作的较早执行时刻之间的默认持续时间的方法中，其中该存储元件可在测试操作模式和正常操作模式下操作，首先，在测试操作模式期间确定和提供存储器元件中的实时持续时间，其中选择实时持续时间，使得当使用第一时钟的执行时刻之间的实时持续时间时，存储器元件的性能参数并且第二操作改进了使用第一操作和第二操作的执行时刻之间的默认持续时间的情况。然后，在测试操作模式期间，在实时持续时间的方向上改变默认持续时间，以获得修改的默认持续时间。然后，在测试操作模式期间将关于修改的默认持续时间或所确定的实时持续时间的信息存储在存储器元件中，其中第二操作被执行偏移了在第一操作期间的执行时刻之后的修改的默认持续时间正常运行模式。

58. 发明授权

US06721219B2 Method and circuit arrangement for reading out and for storing binary memory cell signals 失效
标题翻译：用于读出和存储二进制存储单元信号的方法和电路装置
公开(公告)号：US06721219B2
公开(公告)日：2004-04-13
申请号：US10150340
申请日：2002-05-17
申请人： Athanasia Chrysostomides , Sabine Kling , Peter Pfefferl , Dominique Savignac , Helmut Schneider
发明人： Athanasia Chrysostomides , Sabine Kling , Peter Pfefferl , Dominique Savignac , Helmut Schneider
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C2207/002
摘要： The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.
摘要翻译：本发明提供一种方法，其中来自a的二进制存储单元信号，至少一个存储单元被施加到至少一个位线对（201t，201b），来自存储器的二进制存储器单元信号经由位线对（201t，201b）被切换到至少一个读出放大器（202）将读出放大器（202）的二进制输出信号作为二进制中间信号切换到本地数据线对（205），将本地数据线对（205）上的二进制中间信号切换到至少一个主数据线开关晶体管对（209）以主数据线切换晶体管对（209）的方式依赖于通过行控制线（210）馈送的行控制信号，主数据线开关晶体管对（209）布置在形成在存储单元阵列之间的贯通电镀区域中。

59. 发明授权

US5327072A Regulating circuit for a substrate bias voltage generator 失效
标题翻译：衬底偏置电压发生器的调节电路
公开(公告)号：US5327072A
公开(公告)日：1994-07-05
申请号：US839787
申请日：1992-02-21
申请人： Dominique Savignac , Manfred Menke , Dieter Gleis
发明人： Dominique Savignac , Manfred Menke , Dieter Gleis
IPC分类号： G06F15/78 , G05F3/20 , G11C5/14 , G11C11/407 , G11C11/408 , G11C11/413 , G05F3/16 , H03L1/00
CPC分类号： G05F3/205 , G11C5/146
摘要： A regulating circuit for a substrate bias voltage generator for generating a substrate bias voltage in an integrated semiconductor circuit includes a Schmitt trigger circuit disposed between a first potential and a second potential of a semiconductor circuit. The Schmitt trigger circuit has an output side and an input for controlling a hysteresis function of the Schmitt trigger circuit. An inverter array is connected downstream of the output side of the Schmitt trigger circuit. The inverter array is connected to the first potential and to a first supply potential of the semiconductor circuit in terms of supply voltage, and the inverter array has an output. The input of the Schmitt trigger circuit for controlling the hysteresis function of the Schmitt trigger circuit is connected to the output of the inverter array.
摘要翻译：用于在集成半导体电路中产生衬底偏置电压的衬底偏置电压发生器的调节电路包括设置在半导体电路的第一电位和第二电位之间的施密特触发电路。施密特触发电路具有输出端和用于控制施密特触发电路的滞后功能的输入端。逆变器阵列连接在施密特触发电路输出侧的下游。逆变器阵列在电源电压方面连接到半导体电路的第一电位和第一电源电位，并且逆变器阵列具有输出。用于控制施密特触发电路的滞后功能的施密特触发电路的输入连接到逆变器阵列的输出。

60. 发明授权

US5166546A Integrated circuit for generating a reset signal 失效
标题翻译：用于产生复位信号的集成电路
公开(公告)号：US5166546A
公开(公告)日：1992-11-24
申请号：US823860
申请日：1992-01-22
申请人： Dominique Savignac , Dieter Gleis , Brian Murphy
发明人： Dominique Savignac , Dieter Gleis , Brian Murphy
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.
摘要翻译：用于产生复位信号的集成电路包括用于第一和第二电源电位的端子。终端之间连接有一个串行RC网络。 RC网络具有连接在组件之间的集成电路的欧姆分量，电容分量和第一电路节点。初始化电路与RC网络并联连接。初始化电路具有形成集成电路的第二电路节点的输出，该第一电路节点在施加第一电源电位时承载具有由初始化电路的尺寸确定的最大值的电位。在电源电压方面，逆变器电路连接在第一电路节点和用于第二电源电位的端子之间。逆变器电路具有连接到第二电路节点的输入端和形成集成电路的第三电路节点的输出。晶体管具有连接在第二电路节点和用于第二电源电位的端子之间的源极至漏极路径，并且具有连接到第三电路节点的栅极。附加的反相器具有在第三电路节点处的输入和形成集成电路的第四电路节点的输出，在该输出端处在操作期间存在复位信号。

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