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51. 发明授权

US07372917B2 Digital algorithm for on-line ACPR optimization in polar RF transmitters 失效
标题翻译：极地射频发射机在线ACPR优化的数字算法
公开(公告)号：US07372917B2
公开(公告)日：2008-05-13
申请号：US10944551
申请日：2004-09-17
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04L25/49 , H04B1/04
CPC分类号： H04L27/361 , H03C5/00 , H03F1/3252 , H04L27/2078 , H04L27/368
摘要： An RF transmitter includes a digital processor that includes a time shift signal determination block that produces a time shift signal based upon a bleed over power level in an adjacent channel resulting from downstream phase and magnitude mismatch of a primary signal. In one embodiment, the time shift signal determination block includes logic and circuitry for determining a power ratio for a primary signal between a bleed over power level in an adjacent channel and the primary channel. The time shift signal determination block produces the time shift signal to a time shift block that is operably coupled to receive one of an envelope magnitude component and a phase component from a digital signal generation block, wherein the time shift block generates a time shift in at least one of the envelope signal path and the phase signal path based upon the time shift signal.
摘要翻译： RF发射机包括数字处理器，该数字处理器包括时移信号确定块，该时移信号确定块基于由主信号的下游相位和幅度失配导致的相邻信道中的功率电平渗漏而产生时移信号。在一个实施例中，时移信号确定块包括逻辑和电路，用于确定相邻信道中的渗出功率电平与主信道之间的主信号的功率比。时移信号确定块产生时移信号到时移模块，该时移块可操作地耦合以从数字信号产生块接收包络幅度分量和相位分量中的一个，其中该时移块产生在基于时移信号的包络信号路径和相位信号路径中的至少一个。

52. 发明授权

US07324789B2 PLL frequency synthesizer architecture for low phase noise and reference spurs 有权
标题翻译： PLL频率合成器架构，用于低相位噪声和参考杂散
公开(公告)号：US07324789B2
公开(公告)日：2008-01-29
申请号：US11039116
申请日：2005-01-20
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04B1/40
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/1976
摘要： A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by using a digital processor to generate a digital reference signal at a finely-tuned reference frequency. A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal, and a low pass filter filters the analog reference signal to produce a filtered analog reference signal. The frequency synthesizer further includes a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal.
摘要翻译：在收发器中使用的频率合成器通过使用数字处理器以精细调谐的参考频率产生数字参考信号，产生具有精细频率分辨率和低带内相位噪声的相对高的参考频率。数模转换器（DAC）将数字参考信号转换为模拟参考信号，低通滤波器对模拟参考信号进行滤波以产生滤波后的模拟参考信号。频率合成器还包括用于将经滤波的模拟参考信号从IF信号上变频到RF信号的锁相环。

53. 发明授权

US07116729B2 Trimming of local oscillation in an integrated circuit radio 有权
公开(公告)号：US07116729B2
公开(公告)日：2006-10-03
申请号：US10243861
申请日：2002-09-13
申请人： Brima Ibrahim , Henrik T. Jensen
发明人： Brima Ibrahim , Henrik T. Jensen
IPC分类号： H04L27/14 , H04L27/16 , H04L27/22
CPC分类号： H04L25/061 , H04L25/063 , H04L27/0014 , H04L2027/003 , H04L2027/0053 , H04L2027/0065
摘要： A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

54. 发明授权

US07102547B2 Method of near-unity fractional sampling rate alteration for high fidelity digital audio 有权
$Method of near-unity fractional sampling rate alteration for high fidelity digital audio$
标题翻译：高保真数字音频接近一致分数采样率变化的方法
公开(公告)号：US07102547B2
公开(公告)日：2006-09-05
申请号：US11069364
申请日：2005-03-01
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M7/00
CPC分类号： H03H17/028 , G11B20/10 , G11B20/10527 , G11B2020/10546 , G11B2220/2545 , G11B2220/913
摘要： The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.
摘要翻译：本发明提供了在诸如CD到DAT转换的高性能应用中的近乎一致的采样率改变的有效方法。具体地，输入数字信号首先被插值8倍，并且被低通滤波以形成中间信号。然后采用钳位三次样条内插器（CCSI）算法将中间信号精确地插入中间信号的相邻采样点之间，按照48 kHz输出采样率的要求。由于重复的理查森外推法得到的高精度衍生值估计，CCSI是高度准确的。在详细描述的示例CD到DAT转换器中，采用四阶理查森外推法。由该示例示出，所提出的方法产生期望的性能，在计算上是有效的并且几乎不需要存储。

55. 发明申请

US20060077010A1 Phase locked loop modulator calibration techniques 有权
公开(公告)号：US20060077010A1
公开(公告)日：2006-04-13
申请号：US11281165
申请日：2005-11-16
申请人： Henrik T. Jensen , Hea Joung Kim
发明人： Henrik T. Jensen , Hea Joung Kim
IPC分类号： H03L7/00
CPC分类号： H03C3/0991 , H03L7/0898
摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

56. 发明授权

US06880262B1 Continuous time ΔΣ ADC with dithering 失效
标题翻译：连续时间ΔSigmaADC具有抖动
公开(公告)号：US06880262B1
公开(公告)日：2005-04-19
申请号：US10676320
申请日：2003-09-30
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M3/00 , H03M1/12
CPC分类号： H03M3/332 , H03M3/406 , H03M3/424
摘要： The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CTΔΣADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CTΔΣADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CTΔΣADC loop. In one embodiment of the invention, random noise is added to the quantizer input. In another embodiment, a relatively small amount of current is randomly added or subtracted in the feedback loop to randomize and de-correlate the quantization noise from the input signal while maintaining required signal to noise ratios.
摘要翻译：本发明采用数字信号处理和模拟电路的混合来减少连续时间ΔΣ模数转换器（CTDeltaSigmaADC）中的杂散噪声。具体地，将少量随机加性噪声（也称为抖动）引入到CTDeltaSigmaADC中，以通过使来自输入信号的量化噪声随机化和解相关而不显着降低SNR性能来改善线性行为。在每个实施例中，数字电路用于产生抖动的期望随机性，去相关性和光谱形状，并且使用简单的模拟电路块来适当地缩放并将抖动注入到CTDeltaSigmaADC环路中。在本发明的一个实施例中，随机噪声被加到量化器输入端。在另一个实施例中，在反馈环路中随机地增加或减少相对较少量的电流，以便在保持所需的信噪比的同时使来自输入信号的量化噪声随机化和解相关。

57. 发明授权

US06870492B1 Method of near-unity fractional sampling rate alteration for high fidelity digital audio 失效
$Method of near-unity fractional sampling rate alteration for high fidelity digital audio$
公开(公告)号：US06870492B1
公开(公告)日：2005-03-22
申请号：US10821056
申请日：2004-04-08
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： G11B20/10 , H03H17/06 , H03M7/00
CPC分类号： H03H17/028 , G11B20/10 , G11B20/10527 , G11B2020/10546 , G11B2220/2545 , G11B2220/913
摘要： The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

58. 发明授权

US06819910B2 Radio employing a self calibrating transmitter with reuse of receiver circuitry 失效
标题翻译：无线电采用自动校准发射机，重复使用接收机电路
公开(公告)号：US06819910B2
公开(公告)日：2004-11-16
申请号：US10094495
申请日：2002-03-08
申请人： Hong Shi , Henrik T. Jensen
发明人： Hong Shi , Henrik T. Jensen
IPC分类号： H04B104
CPC分类号： H04B1/406
摘要： A radio includes a self-calibrating transmitter that uses a portion of a receiver section to perform self-calibration. Accordingly, the radio includes a transmitter section, mixer, analog receiver section, calibration switch module, digital receiver section, calibration determination module, and calibration execution module. The transmitter section produces a modulated RF signal from base-band signal and a transmitter local oscillation. The mixer mixes the modulated RF signal with the transmitter local oscillation to produce a base-band representation of the modulated RF signal. In calibration mode, the calibration switch module provides the base-band representation to the receiver section, which processes the representation to produce a 2nd base-band digital signal. The calibration determination module interprets frequency components of the 2nd base-band digital signal to produce a calibration signal that compensates for imbalances within the transmitter.
摘要翻译：收音机包括使用接收器部分的一部分来执行自校准的自校准发射器。因此，无线电设备包括发射机部分，混合器，模拟接收机部分，校准开关模块，数字接收机部分，校准确定模块和校准执行模块。发射机部分从基带信号和发射机本地振荡产生调制的RF信号。混频器将调制的RF信号与发射机本地振荡器混合，以产生调制的RF信号的基带表示。在校准模式下，校准开关模块向接收器部分提供基带表示，其处理该表示以产生第二基带数字信号。校准确定模块解释第二基带数字信号的频率分量以产生补偿发射机内的不平衡的校准信号。

59. 发明授权

US06781533B2 Optically sampled delta-sigma modulator 失效
标题翻译：光学采样Δ-Σ调制器
公开(公告)号：US06781533B2
公开(公告)日：2004-08-24
申请号：US10281331
申请日：2002-10-25
申请人： Daniel Yap , Henrik T. Jensen
发明人： Daniel Yap , Henrik T. Jensen
IPC分类号： H03M300
CPC分类号： H03M3/496 , H03M3/43 , H03M3/456
摘要： A delta-sigma modulator has a first node at which is produced a difference signal equal to the difference in magnitude between a continuous time analog signal and an analog feedback signal generated from a digital output signal; an integrator, coupled to the first node, to integrate the difference signal, thereby producing a first integrated signal; a photonic sampler, coupled to the integrator, to sample the first integrated signal, thereby producing a sampled integral signal; a quantizer, coupled to the sampler, to quantize the sampled integral signal, thereby producing the digital output signal; wherein an output of the quantizer is coupled to the first node through a digital to analog converter.
摘要翻译： Δ-Σ调制器具有第一节点，在该第一节点处产生等于连续时间模拟信号和从数字输出信号产生的模拟反馈信号之间的幅度差的差信号; 耦合到第一节点的积分器，以整合差分信号，从而产生第一集成信号; 耦合到积分器的光子采样器对第一集成信号进行采样，从而产生采样的积分信号; 耦合到采样器的量化器，以量化采样的积分信号，从而产生数字输出信号; 其中所述量化器的输出通过数模转换器耦合到所述第一节点。

60. 发明授权

US07944376B2 Technique for improving modulation performance of translational loop RF transmitters 有权
标题翻译：提高平移环路射频发射机调制性能的技术
公开(公告)号：US07944376B2
公开(公告)日：2011-05-17
申请号：US12533808
申请日：2009-07-31
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M7/00
CPC分类号： H04L27/368
摘要： A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.
摘要翻译：由平移环型RF发射机中的基带处理器产生的发送信号被“预失真”，以抵消由窄PLL信号滤波器施加的动作幅度失真和组延迟变化。预失真发生在两个步骤中：基带处理器中的幅度均衡器根据PLL信号滤波器幅度响应的倒数来预失真发射信号的幅度，并且组延迟均衡器将整个发射机的相位响应线性化链，即，预发射发射信号，使得幅度均衡器，组延迟均衡器和PLL信号滤波器的组合相位响应是线性的。通过这种预失真，提供了一个环路滤波器，用于为分频值定义一个相对较小的带宽，以将由IF参考馈通产生的杂散音调滤波到平移回路的压控振荡器。

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