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    • 51. 发明授权
    • Storage device backplane and identification circuit
    • 存储设备背板和识别电路
    • US08045336B2
    • 2011-10-25
    • US12025505
    • 2008-02-04
    • Lan HuangShih-Hao Liu
    • Lan HuangShih-Hao Liu
    • H05K1/11H05K1/14
    • G06F13/409G06F13/4247
    • A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number.
    • 提供了存储设备背板和用于识别存储设备背板的使用情况的识别电路。 存储设备背板具有第一连接接口和第二连接接口,用于作为支撑母板的第一背板或级联到第一背板的第二背板或支撑母板的子板的第一背板。 第一和第二背板具有相同的存储设备背板结构。 如果存储设备背板用作第一背板,则第一背板的第一连接接口耦合到主板或其母板; 如果存储设备背板用作第二背板,则第二背板的第一连接接口耦合到第一背板的第二连接接口。 识别电路识别存储设备背板的使用情况,并显示相应的正确指示器编号。
    • 53. 发明授权
    • Core voltage controlling apparatus
    • 核心电压控制装置
    • US07853810B2
    • 2010-12-14
    • US11960178
    • 2007-12-19
    • Lan HuangShih-Hao Liu
    • Lan HuangShih-Hao Liu
    • G06F1/26
    • G06F1/26
    • A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.
    • 提供一种适用于中央处理单元(CPU)的核心电压控制装置。 该装置包括电平转换单元,延时单元和逻辑单元。 电平移位单元的输入端子接收并移位第一电压信号,并且输出端子产生其中第一电压信号指示通电稳定状态的第二电压信号,并且第二电压信号指示第 核心电压。 时间延迟单元延迟第二电压信号以产生第三电压信号。 逻辑单元耦合到时间延迟单元,用于对由电源发送的第三电压和第四电压信号进行逻辑运算,并产生用于控制核心电压发生器的第五电压信号,以提供核心电压 CPU,否则,第四电压信号表示电源状态。
    • 55. 发明授权
    • Memory reset apparatus
    • 存储器复位装置
    • US07616039B2
    • 2009-11-10
    • US11970962
    • 2008-01-08
    • Lan HuangShih-Hao Liu
    • Lan HuangShih-Hao Liu
    • H03K3/02G06F13/00
    • G11C5/063H03K17/22
    • A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.
    • 提供了包括第一反向电路,逻辑电路和多个第二反向电路的存储器复位装置。 第一反向电路接收由北桥产生的控制信号,并产生第一信号,其中控制信号控制多个存储器的复位。 逻辑电路执行第一信号和指示信号的逻辑运算,并产生第二信号,其中指示信号指示计算机系统的每个部件完全通电。 多个第二反向电路分别耦合在逻辑电路和存储器之间。 第二反向电路与第二信号反相并分别产生多个复位信号给存储器,从而复位存储器。