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51. 发明授权

US10159122B2 System and method for emulating a gas discharge lamp 有权
公开(公告)号：US10159122B2
公开(公告)日：2018-12-18
申请号：US13530544
申请日：2012-06-22
申请人： Nan Chen , Shu-Hung Henry Chung
发明人： Nan Chen , Shu-Hung Henry Chung
IPC分类号： H05B33/08 , H05B37/02
摘要： A system and method for emulating a gas discharge lamp comprising an input arranged to direct electric current from a lamp ballast to a delay circuit, wherein the delay circuit is arranged to establish an electrical communication between the lamp ballast and an electric lamp when a predetermined condition associated with one or more characteristics of the gas discharge lamp is attained.

52. 发明授权

US09921203B2 Method for predicting sediment content of a hydroprocessed hydrocarbon product 有权
公开(公告)号：US09921203B2
公开(公告)日：2018-03-20
申请号：US13294566
申请日：2011-11-11
申请人： Estrella Rogel , Cesar Ovalles , Pak Leung , Nan Chen
发明人： Estrella Rogel , Cesar Ovalles , Pak Leung , Nan Chen
IPC分类号： G01N31/00 , G01N33/28 , G01N30/86 , G01N30/88
CPC分类号： G01N33/2823 , G01N30/8631 , G01N33/2829 , G01N2030/8854
摘要： Disclosed herein is a method of predicting sediment content of a hydroprocessed hydrocarbon product. The method involves: (a) precipitating an amount of asphaltenes from a liquid sample of a first hydrocarbon-containing feedstock having solvated asphaltenes therein with one or more first solvents; (b) determining one or more solubility characteristics of the precipitated asphaltenes; (c) analyzing the one or more solubility characteristics; (d) determining asphaltene content of the liquid sample from the results of analyzing the one or more solubility characteristics; (e) determining one or more asphaltene stability parameters of the liquid sample from the results of analyzing the one or more solubility characteristics; and (f) correlating the asphaltene content and one of the asphaltene stability parameters of the liquid sample with at least two operation conditions associated with a refinery to predict sediment content.

53. 发明授权

US08707001B2 Method and system for measuring memory access time using phase detector 失效
标题翻译：使用相位检测器测量存储器存取时间的方法和系统
公开(公告)号：US08707001B2
公开(公告)日：2014-04-22
申请号：US12328283
申请日：2008-12-04
申请人： Nan Chen , Zhiqin Chen , Varun Verma
发明人： Nan Chen , Zhiqin Chen , Varun Verma
IPC分类号： G06F12/00
CPC分类号： G11C29/50 , G01R31/31725 , G11C7/22 , G11C29/50012 , G11C29/56 , G11C29/56012
摘要： Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.
摘要翻译：提供了用于确定存储器访问时间的方法和系统。在存储器使用的第一时钟信号和用作参考时钟信号的第二时钟信号之间测量第一相位偏移。然后，当存储器完成给定读取操作和第二时钟信号时，在由存储器输出的第一时钟信号的延迟版本之间测量第二相位偏移。存储器访问时间基于第一和第二相位偏移来确定。

54. 发明申请

US20130124105A1 METHOD FOR PREDICTING SEDIMENT CONTENT OF A HYDROPROCESSED HYDROCARBON PRODUCT 有权
标题翻译：用于预测氢化烃产品的含量的方法
公开(公告)号：US20130124105A1
公开(公告)日：2013-05-16
申请号：US13294566
申请日：2011-11-11
申请人： Estrella Rogel , Cesar Ovalles , Pak Leung , Nan Chen
发明人： Estrella Rogel , Cesar Ovalles , Pak Leung , Nan Chen
IPC分类号： G01N30/02 , G06F19/00
CPC分类号： G01N33/2823 , G01N30/8631 , G01N33/2829 , G01N2030/8854
摘要： Disclosed herein is a method of predicting sediment content of a hydroprocessed hydrocarbon product. The method involves: (a) precipitating an amount of asphaltenes from a liquid sample of a first hydrocarbon-containing feedstock having solvated asphaltenes therein with one or more first solvents; (b) determining one or more solubility characteristics of the precipitated asphaltenes; (c) analyzing the one or more solubility characteristics; (d) determining asphaltene content of the liquid sample from the results of analyzing the one or more solubility characteristics; (e) determining one or more asphaltene stability parameters of the liquid sample from the results of analyzing the one or more solubility characteristics; and (f) correlating the asphaltene content and one of the asphaltene stability parameters of the liquid sample with at least two operation conditions associated with a refinery to predict sediment content.
摘要翻译：本文公开了一种预测加氢烃产物的沉淀物含量的方法。该方法包括：（a）从具有溶剂化沥青质的第一含烃原料的液体样品中用一种或多种第一溶剂沉淀出一定量的沥青质; （b）确定沉淀的沥青质的一种或多种溶解度特性; （c）分析一种或多种溶解度特性; （d）从分析一种或多种溶解度特征的结果确定液体样品的沥青质含量; （e）从分析一种或多种溶解度特征的结果确定液体样品的一种或多种沥青质稳定性参数; 和（f）使沥青质含量和液体样品的沥青质稳定性参数之一与至少两个与炼油厂相关的操作条件相关以预测沉积物含量。

55. 发明授权

US08289090B2 Amplitude control for oscillator 失效
标题翻译：振荡器幅度控制
公开(公告)号：US08289090B2
公开(公告)日：2012-10-16
申请号：US12886719
申请日：2010-09-21
申请人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
发明人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
IPC分类号： H03B5/36 , H03G1/00 , H03L5/00
CPC分类号： H03L5/00 , H03B5/36 , H03L3/00
摘要： An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.
摘要翻译：振幅控制电路包括一对峰值检测器。一对峰值检测器响应于电压参考发生器。幅度控制电路被配置为响应于晶体振荡器的振荡信号，并被配置为产生控制信号以控制振荡信号的振幅。

56. 发明授权

US07859920B2 Advanced bit line tracking in high performance memory compilers 有权
标题翻译：高性能内存编译器中的高级位线跟踪
公开(公告)号：US07859920B2
公开(公告)日：2010-12-28
申请号：US12048676
申请日：2008-03-14
申请人： Chang Ho Jung , Nan Chen , Zhiqin Chen
发明人： Chang Ho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/14 , G11C7/08 , G11C7/22
摘要： A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling of the dummy word line. The dummy bit line matures at a same rate that a real bit line matures. The method also includes disabling the dummy word line in response to determining a threshold voltage differential based on monitoring maturation of the dummy bit line. The real word line is enabled a predefined delay after enabling of the dummy word line. Similarly, the word line is disabled the predefined delay after disabling of the dummy word line. In response to disabling the dummy word line, a sense enable signal is generated.
摘要翻译：一种方法准确地跟踪编译器存储器的位线成熟时间。该方法包括响应于内部时钟信号启用伪字线。虚拟字线在启用实际字线之前被使能。虚拟位线响应于虚拟字线的使能而成熟。虚拟位线以与实际位线成熟的相同速率成熟。该方法还包括响应于基于虚拟位线的监视成熟确定阈值电压差来禁用该虚拟字线。在使能虚拟字线之后，实际字线被启用预定义的延迟。类似地，在禁用虚拟字线之后，字线被禁用预定义的延迟。响应于禁用虚拟字线，产生感测使能信号。

57. 发明申请

US20100238756A1 Self Reset Clock Buffer In Memory Devices 有权
标题翻译：内存器件中的自复位时钟缓冲器
公开(公告)号：US20100238756A1
公开(公告)日：2010-09-23
申请号：US12792982
申请日：2010-06-03
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/18 , H03K19/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.
摘要翻译：存储器件包括时钟缓冲电路。时钟缓冲电路包括交叉耦合逻辑电路。交叉耦合逻辑电路具有至少两个逻辑门，其中至少一个逻辑门的输出耦合到至少一个逻辑门的输入。交叉耦合逻辑电路耦合到用于接受时钟信号的输入端。该存储器件还包括一个可从交叉耦合逻辑电路的输出产生时钟信号的时钟驱动器。从时钟信号到交叉耦合逻辑电路的反馈环路控制交叉耦合逻辑电路。包括三态反相器的缓冲电路耦合到时钟信号以保持时钟信号，同时避免与时钟发生器的争用。存储器件通过芯片选择信号使能。

58. 发明申请

US20100046280A1 SRAM Yield Enhancement by Read Margin Improvement 有权
标题翻译：通过读保留期改进提高SRAM产量
公开(公告)号：US20100046280A1
公开(公告)日：2010-02-25
申请号：US12194142
申请日：2008-08-19
申请人： Nan Chen , Chang Ho Jung , Zhiqin Chen
发明人： Nan Chen , Chang Ho Jung , Zhiqin Chen
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C11/409 , G11C2207/005
摘要： A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.
摘要翻译：针对存储器阵列中的读取路径改进了检测边缘。实施例通过在读列多路复用器中使用具有较低阈值电压的门来提高感测余量。交叉耦合保持器可以通过增加存储高值的位线上的电压电平来进一步提高感测容限，从而抵消“高”位线上的泄漏。

59. 发明申请

US20080285367A1 METHOD AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN MEMORY ARRAYS 审中-公开
标题翻译：用于减少存储器阵列漏电流的方法和装置
公开(公告)号：US20080285367A1
公开(公告)日：2008-11-20
申请号：US11750505
申请日：2007-05-18
申请人： Chang Ho Jung , Nan Chen , Zhiqin Chen
发明人： Chang Ho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C7/10
CPC分类号： G11C7/22
摘要： Techniques for reducing leakage current in memory arrays are described. A memory array has multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to a power supply and float during a sleep mode for the memory array. The bit lines may be coupled to (i) precharge circuits used to precharge the bit lines prior to each read or write operation, (ii) pass transistors used to couple the bit lines to sense amplifiers for read operations, and (iii) pull-up transistors in drivers used to drive the bit lines for write operations. The precharge circuits, pass transistors, and pull-up transistors are turned off during the sleep mode. The word lines are set to a predetermined logic level to disconnect the memory cells from the bit lines during the sleep mode.
摘要翻译：描述了用于减少存储器阵列中的漏电流的技术。存储器阵列具有多行和多列存储单元。位线耦合到存储器单元的列，并且字线耦合到存储器单元的行。在存储器阵列的休眠模式期间，位线已断开到电源的路径和浮动。位线可以耦合到（i）用于在每次读取或写入操作之前对位线预充电的预充电电路，（ii）将用于将位线耦合到感测放大器的晶体管用于读取操作，以及（iii）用于驱动位线用于写操作的驱动器中的上拉晶体管。在睡眠模式期间，预充电电路，传输晶体管和上拉晶体管截止。字线被设置为预定的逻辑电平以在睡眠模式期间将存储器单元与位线断开。

60. 发明授权

US07092307B2 Leakage current reduction for CMOS memory circuits 有权
标题翻译： CMOS存储器电路的泄漏电流降低
公开(公告)号：US07092307B2
公开(公告)日：2006-08-15
申请号：US10641883
申请日：2003-08-14
申请人： Nan Chen , Cheng Zhong , Mehdi Hamidi Sani
发明人： Nan Chen , Cheng Zhong , Mehdi Hamidi Sani
IPC分类号： G11C5/14
CPC分类号： G11C11/4074 , G11C11/413 , G11C2207/2227
摘要： A CMOS integrated circuit (e.g., an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e.g., memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The peripheral block includes circuits that may be powered on or off and are coupled to the power supply via a head switch and/or to circuit ground via a foot switch. The switches and the core block may be implemented with high threshold voltage (high-Vt) FET devices to reduce leakage current. The peripheral block may be implemented with low-Vt FET devices for high-speed operation. The retention block includes circuits (e.g., pull-up devices) that maintain signal lines (e.g., word lines) at a predetermined level so that the internal states of the core block are retained when the peripheral block is powered off.
摘要翻译： CMOS集成电路（例如，SRAM或DRAM）被划分为核心块，外围块和保留块。核心块包括始终上电并直接耦合到电源和电路接地的电路（例如，存储器单元）。外围块包括可以通电或断开并且经由头开关耦合到电源和/或经由脚踏开关电路接地的电路。开关和核心块可以用高阈值电压（高Vt）FET器件来实现，以减少泄漏电流。外围块可以用用于高速操作的低Vt FET器件来实现。保持块包括将信号线（例如，字线）保持在预定水平的电路（例如，上拉装置），使得当外围块被断电时，芯块的内部状态被保持。

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