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51. 发明专利

JP2591468B2 失效
公开(公告)号：JP2591468B2
公开(公告)日：1997-03-19
申请号：JP8128694
申请日：1994-04-20
申请人： HITACHI LTD
发明人： MYAZAWA KAZUYUKI , SHIMOHIGASHI KATSUHIRO , ETO JUN , KIMURA KATSUTAKA
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C29/00 , G11C29/34

52. 发明专利

JPH0969067A SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSOR 失效
公开(公告)号：JPH0969067A
公开(公告)日：1997-03-11
申请号：JP24695695
申请日：1995-08-31
申请人： HITACHI LTD
发明人： NAKAMURA YASUHIRO , FURUSAWA KAZUNORI , ETO JUN , IZAWA KAZUTO , YUGAWA YOSUKE , KOSAKAI KENJI
IPC分类号： G06F12/14 , G06F21/24 , G11C16/02 , G11C16/06 , G11C17/00
摘要： PROBLEM TO BE SOLVED: To actualize a security protecting function in a semiconductor memory chip by comparing a password written in a register with an externally inputted password and deciding whether or not a read of data from a memory cell array is allowed. SOLUTION: The semiconductor storage device is constituted including the register 20 where a password can be set, a password deciding means which decides whether or not the password set in the register 20 matches an externally inputted password, and a control means which allows or inhibit a data read from the memory cell array 13 according to the decision result of the password deciding means. Then this control means allows or inhibits the data read from the memory cell array 13 according to the decision result showing whether or not the password set in the register 20 matches the externally inputted password. Thus, the security protecting function is displayed in the semiconductor storage device.

53. 发明专利

JPH0831270B2 失效
公开(公告)号：JPH0831270B2
公开(公告)日：1996-03-27
申请号：JP17992486
申请日：1986-08-01
申请人： HITACHI LTD
发明人： ETO JUN , KIMURA KATSUTAKA , SHIMOHIGASHI KATSUHIRO , MYAZAWA KAZUYUKI
IPC分类号： G11C11/401 , G11C11/34 , G11C11/409 , H01L21/8242 , H01L27/108

54. 发明专利

JPH06243690A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06243690A
公开(公告)日：1994-09-02
申请号：JP32682193
申请日：1993-12-24
申请人： HITACHI LTD
发明人： MATSUNO KATSUMI , TAKEUCHI MIKI , OJI YUZURU , AOKI MASAKAZU , ETO JUN , SAKATA TAKESHI , HORIGUCHI SHINJI
IPC分类号： G11C14/00 , G11C11/22
摘要： PURPOSE:To obtain a semiconductor memory using a ferroelectric substance in which power consumption is small. CONSTITUTION:In a semiconductor memory using a ferroelectric substance, after a data line selecting means selects one data line (DLfj), a pre-charge means (PCf0) sets a potential of the selected one data line (DLfj) to a first potential (VDD). And a word line selecting means activates one word line (WLfi). Thereby, a non-selected data line is not required to charge previously to the first potential (VDD), and power consumption can be made small.

55. 发明专利

JPH0334188A MEMORY CIRCUIT 失效
公开(公告)号：JPH0334188A
公开(公告)日：1991-02-14
申请号：JP16664889
申请日：1989-06-30
申请人： HITACHI LTD
发明人： ETO JUN , ITO KIYOO , KAWAJIRI YOSHIKI
IPC分类号： G11C11/404
摘要： PURPOSE:To drastically reduce power consumption while the accumulated voltage of a memory cell being secured sufficiently by lowering data line voltage amplitude down to a value a little larger than the threshold voltage of an MOSFET to constitute a sense amplifier at the time the amplification of a memory cell signal. CONSTITUTION:The data line voltage amplitude at the time of the amplification of the memory cell MC signal is lowered down to the vicinity of the threshold voltage of the MOSFET TO constitute the sense amplifier SA. Thus, a data line charging/discharging current can be reduced remarkable, and the power consumption can be reduced. By lowering the data line voltage amplitude, voltage to be written in the memory cell MC from a data line is lowered, but the memory cell signal can be made large by boosting this voltage from one end of a capacitor to constitute the memory cell MC. Accordingly, an information holding characteristic and S/M can be improved.

56. 发明专利

JPH02244817A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02244817A
公开(公告)日：1990-09-28
申请号：JP6364489
申请日：1989-03-17
申请人： HITACHI LTD
发明人： KUME EIJI , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , AOKI MASAKAZU , ITO KIYOO
IPC分类号： G11C11/407 , H03K5/02 , H03K19/0185
摘要： PURPOSE:To reduce a through current that flows on a level conversion circuit used as an input signal to a circuit operated by a high voltage power source by using the complementary output signal of the circuit operated by a low voltage power source and the level conversion circuit having a latch function. CONSTITUTION:The title circuit is provided with a low voltage generation circuit 2 to decrease a source voltage outside a chip, the circuit 3 operated by using a decreased low voltage, and an output circuit 5 operated by using an external source voltage. And the level conversion circuit 9 operated by the external source voltage and controlled by the complementary output signal from the low voltage circuit 3 is provided between the low voltage circuit 3 and the output circuit 5. Namely, the voltage of the output signal with low amplitude of the circuit 3 operated by the low voltage power source can be increased to and latched at the voltage level of the circuit 5 operated by the high voltage power source. Therefore, the input level of a CMOS inverter in the high voltage power source operation circuit 5 goes to an intermediate value, and the through current can be prevented from being continued to flow. In such a way, the through current can be reduced.

57. 发明专利

JPH02172093A SEMICONDUCTOR MEMORY DRIVE SYSTEM 失效
公开(公告)号：JPH02172093A
公开(公告)日：1990-07-03
申请号：JP32578388
申请日：1988-12-26
申请人： HITACHI LTD
发明人： KUME EIJI , ITO KIYOO , ETO JUN
IPC分类号： G11C11/409
摘要： PURPOSE:To prevent the deterioration in the S/N of a sense amplifier by controlling an operation start time and an operation speed in response to the resistivity of a MOS transistor (TR) being component of a PMOS amplifier and an NMOS amplifier respectively. CONSTITUTION:Suppose that a parasitic capacitance C1 of a data line 1 is less than a parasitic capacitance C2 of a data line 2, then the charging speed of the data line 1 is going to be faster as the amplification is advanced and the discharge speed of the data line 2 slows down. However, since the gate level of a PMOS TR QP1 of the PMOS amplifier SAP is the level of the data line 2, the increase in a current IP1 is less by the slow-down of the voltage drop of the data line 2 to suppress the charging speed of the data line 1 from being increase. On the other hand, the gate level of an NMOS TR QN2 of the NMOS amplifier SAN is a level of the data line 1, the increase in the current IN2 is large to suppress the discharge speed of the data line 2 from slowing down. Thus, the level of the data lines 1,2 is inverted to prevent malfunction and the deterioration the S/N of the sense amplifier is prevented.

58. 发明专利

JPH01159889A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01159889A
公开(公告)日：1989-06-22
申请号：JP31620487
申请日：1987-12-16
申请人： HITACHI LTD
发明人： ETO JUN , HORI RYOICHI , ITO KIYOO , AOKI MASAKAZU , HONMA NORIYUKI
IPC分类号： G11C11/409 , G11C11/34 , G11C11/407
摘要： PURPOSE:To eliminate the timing margin of a sense amplifier driving signal and to make the action speed of a memory into a high speed by providing a circuit to detect, that the voltage of a word line exceeds a prescribed degree, to every word line, and operating a sense amplifier based on a detection result. CONSTITUTION:A voltage detecting circuit WS of word lines Wo-Wn detects the voltages of the word lines Wo-Wn to actually select a memory cell MC, and the circuit WS operates sense amplifiers SAo-SAn to amplify a memory cell MC signal. Consequently, when the detected voltages are made into the precharge voltages of data lines Do-Dn or above, the detecting circuit WS outputs a signal to operate the sense amplifiers SAo-SAn to the data line Do--Dn after the memory cell MC signal is read. Thus, the timing margin of the driving signal of the sense amplifiers SAo-SAn can be made unnecessary, and the action speed of the memory can be made into the high speed.

59. 发明专利

JPH01149297A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01149297A
公开(公告)日：1989-06-12
申请号：JP30563887
申请日：1987-12-04
申请人： HITACHI LTD
发明人： ETO JUN , ITO KIYOO , AOKI MASAKAZU , HORI RYOICHI
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12 , G11C11/404 , G11C11/4072 , G11C11/408 , H01L27/10
摘要： PURPOSE:To shorten the time of clear mode operation by providing a circuit to multiple-select a word line, a circuit to multiple-select a data line and a circuit to control the voltage of one edge of a capacitor to constitute a memory. CONSTITUTION:A multiple selecting circuit WM of the word line drives all word line W0 and W1 and causes all memory cells MC to be in a selecting condition. A multiple selecting circuit YDEC of the data line selects all data lines D0, the inverse of D0, D1 and the inverse of D1 and data to be determined in advance can be written through these data lines to the all memory cells MC at once. A voltage control circuit PL of one edge of the capacitor, which constitutes the memory cell MC, boosts a high pressure side out of the voltages to be written through the data lines D0, the inverse of D0, D1 and the inverse of D1 and a writing level is compensated. Thus, the storing data of all the memory cells can be rewritten at once and the time of the clear mode operation can be shortened.

60. 发明专利

JPS63228495A MOS MEMORY 失效
公开(公告)号：JPS63228495A
公开(公告)日：1988-09-22
申请号：JP6102687
申请日：1987-03-18
申请人： HITACHI LTD
发明人： ETO JUN , SHIMOHIGASHI KATSUHIRO , KIMURA KATSUTAKA
IPC分类号： G11C11/407 , G11C11/34 , G11C11/401 , G11C11/4076 , H01L21/8242 , H01L27/108 , H03K5/133 , H03K5/14
摘要： PURPOSE:To quicken the access time of a memory by using plural internal clock signal generating circuits different in delay time prepared in advance. CONSTITUTION:Circuits 3, 4 use a signal phiA to switch the number of stages of inverters for generating an internal clock signal. That is, the internal clock signal phi3 rises when a signal phi2 is sent from a node A through a node B after the internal clock signal phi2 rises with the signal phiA at a high level. On the other hand, when the signal phiA is at a low level, the signal phi3 rises when the signal phi2 is sent from the node A having a few stage number of inverters through a node C. An internal clock signal phi5 rises when the internal clock signal phi4 is sent from a node D through a node E similarly with the signal phiA at a high level, and rises when the signal is fed from the node D with a few stage number of inverters through a node F with the signal phiA at a low level.

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