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51. 发明专利

JPH1187409A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1187409A
公开(公告)日：1999-03-30
申请号：JP18525998
申请日：1998-06-30
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： MIYAZAKI CHUICHI , AKIYAMA YUKIHARU , SHIBAMOTO MASAKUNI , SHIMOISHI TOMOAKI , ANJO ICHIRO , NISHI KUNIHIKO , NISHIMURA ASAO , TANAKA HIDEKI , KIMOTO RYOSUKE , TSUBOSAKI KUNIHIRO , HASEBE AKIO
IPC分类号： H01L21/60 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To assemble a semiconductor integrated circuit device at a high yield rate by stabilizing the bonding method of a semiconductor chip by a method wherein a wiring is formed on the main surface of a substrate base material, an elastic structure is arranged on the backside of the substrate base material, and an insulating film is formed on the main surface of the wiring. SOLUTION: A plurality of bonding pads 7 are formed in a line in the center part in longitudinal direction of a semiconductor chip 1, and an elastomer 2, which is an elastic structure, is bonded to the main surface of the semiconductor chip 1 excluding the part where the bonding pads 7 are formed. A flexible wiring substrate 3, which is composed of a substrate base material 9 and a wiring 10, is bonded to the main surface of the elastomer 2, the lead 11, which is located on one end of the wiring 10, is connected to the bonding pads 7 of the semiconductor chip 1, and the solder bump 5, provided in the aperture of a solder resist 4 which is the insulating film formed on the backside of the wiring 10, is connected to the bump ground 12 on the other end of the wiring 10.

52. 发明专利

JPH09199523A RESIN-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09199523A
公开(公告)日：1997-07-31
申请号：JP3143997
申请日：1997-01-31
申请人： HITACHI LTD
发明人： OGATA MASAJI , EGUCHI KUNIYUKI , SEGAWA MASANORI , HOZOJI HIROYUKI , ISHII TOSHIAKI , NISHI KUNIHIKO , IWATANI AKIHIKO , IMURA KENICHI
IPC分类号： C08K3/36 , C08G59/20 , C08K9/04 , C08L63/00 , H01L21/56 , H01L23/29 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which shows little thermal stress and has an excellent solder-reflow resistance, an excellent temperature cycle resistance after mounting, an excellent moisture-resistant reliability, etc. SOLUTION: The electrodes 2 of a semiconductor chip 1 are electrically connected to leads 4. At least the circuit forming surface of the chip 1 is sealed with resin composition containing epoxy resin (a), curing agent (b), curing accelerator (c) and inorganic filler (d) as essential components. The epoxy resin (a) contains components selected among bifunctional epoxy resins having biphenyl frames or naphthalene frames and the resin component composed of the epoxy resin (a) and the curing agent (b) has a viscosity not larger than 3 poise at 150 deg.C. The inorganic filler (d) is powder consisting of spherical particles whose average diameter is within the range from 2-20μm and not less than 95% of the particles have particle diameters within the range from 0.1-100μm. Further, the content of the inorganic filler (d) in the whole composition is within the range from 75-92.5vol.%. Moreover, the lowest melting biscosity of the resin composition in a pressurized molding process is not larger than 3000 poise and the thermal expansion coefficient of the resin composition after the pressurized molding is not larger than 1.0×10 / deg.C.

53. 发明专利

JP2585738B2 失效
公开(公告)号：JP2585738B2
公开(公告)日：1997-02-26
申请号：JP19985788
申请日：1988-08-12
申请人： HITACHI LTD
发明人： SAKUTA TOSHUKI , MYAZAWA KAZUYUKI , OGUCHI SATOSHI , KANEDA AIZO , MITANI MASAO , NAKAMURA SHOZO , NISHI KUNIHIKO , MURAKAMI HAJIME
IPC分类号： H01L21/52 , H01L21/60 , H01L23/29 , H01L23/31 , H01L23/50 , H01L27/10

54. 发明专利

JPH08340016A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08340016A
公开(公告)日：1996-12-24
申请号：JP19180296
申请日：1996-07-22
申请人： HITACHI LTD
发明人： SAEKI JUNICHI , KANEDA AIZO , TSUNODA SHIGEHARU , YOSHIDA ISAMU , NISHI KUNIHIKO
IPC分类号： B29C45/26 , B29C45/02 , H01L21/56 , H01L23/50
摘要： PURPOSE: To make production efficiency compatible with quality improvement of a product, by a method wherein resin from a pot is made to flow into a first cavity from the first vertex of the first cavity, resin which is made to flow into a second cavity from the first cavity is made to flow into the vertex of the second cavity from the second vertex of the first cavity. CONSTITUTION: A first gate 4 is arranged at the tip of a runner 3 formed in each pot 2 which runner supplies, with pressure, resin for molding, and a first cavity 5 is arranged to be connected with the first gate 4. A second gate 6 is arranged in the rear of the first cavity 5, i.e., in the downstream side at the supply of resin. A second cavity 7 is arranged to be connected with the second gate 6. A third cavity 9 is arranged, via a third gate 8, in the downstream side of the second cavity 7. The respective pots 2 are mutually connected with each other through pot linkage flow channels 10. Chips 13 are mounted on a lead frame 11, at the positions corresponding to the insides of the respective cavities.

55. 发明专利

JPH08165331A RESIN-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08165331A
公开(公告)日：1996-06-25
申请号：JP30864194
申请日：1994-12-13
申请人： HITACHI LTD
发明人： KOKADO HIROYOSHI , EGUCHI KUNIYUKI , ISHII TOSHIAKI , NAGAI AKIRA , OGINO MASAHIKO , MOGI AKIRA , SUZUKI KAZUHIRO , NISHI KUNIHIKO
IPC分类号： C08L63/00 , C08G59/20 , C08G59/24 , C08G59/40 , H01L23/29 , H01L23/31
摘要： PURPOSE: To obtain a high-reliability resin-sealed semiconductor device by coating or molding a semiconductor device with or in an epoxy resin composition prepared by melt-kneading an epoxy resin represented by a specific formula, a curing agent, a cure accelerator and a filter. CONSTITUTION: 100 pts.wt. biphenyl epoxy resin of formula I (wherein R is H or methyl; and N2 is 0-2) is mixed with 0.5-1.5 equivalents of a curing agent containing a phenol/alkyl ether polycondensate of formula II (wherein m is 1-10), 500-1mmol of a cure accelerator comprising an organophosphorus compound of formula III (wherein X is a quaternary ammonium ion; R is 1-4 C alkyl or alkoxy; and N1 is 1-2) and 50-90vol.%, based on the resin composition, inorganic filler of a particle diameter distribution of 0.1-100μm, the obtained mixture is melt-kneaded, and the obtained solid is ground to obtain an epoxy resin composition sealing material. A silicone chip with aluminum wirings is mounted on a lead frame, subjected to wire bonding, and transfer-molded with this sealing agent to obtain a resin-sealed semiconductor device.

56. 发明专利

JPH08139258A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08139258A
公开(公告)日：1996-05-31
申请号：JP27334894
申请日：1994-11-08
申请人： HITACHI LTD
发明人： NAKAMURA ATSUSHI , NISHI KUNIHIKO
IPC分类号： H01L23/28 , H01L23/50 , H05K1/02 , H05K1/18 , H05K3/34
摘要： PURPOSE: To surely reduce inductance in a power supply or a ground circuit by inserting a short-circuiting pin to a first hole provided in a specified inner lead which becomes a ground wiring and a second hole provided to a package and by connecting it electrically to a ground wiring layer of a printed wiring board. CONSTITUTION: A semiconductor device 1 provided with first and second holes 8, 2a in specified positions in a package 2 and an inner lead 6a which becomes a ground wiring 10a is mounted on a printed wiring board 10. A short-circuiting pin 9 is inserted from the second hole 2a, fit to the first hole 8 of the inner lead 6a, made to pass through the hole 2a of a rear of the package 2, inserted to a through-hole land 10b whereto the ground wiring 10a is applied and connected and fixed by solder Hd. Thereby, an inductance in a power supply or a ground circuit can be surely reduced at a low cost.

57. 发明专利

JPH07193162A BALL-GRID ARRAY SEMICONDUCTOR DEVICE AND MOUNTING SUBSTRATE THEREOF 失效
公开(公告)号：JPH07193162A
公开(公告)日：1995-07-28
申请号：JP33064193
申请日：1993-12-27
申请人： HITACHI LTD
发明人： SUMIYA AKIRO , ANJO ICHIRO , ARITA JUNICHI , KAWAI SUEO , TSUBOSAKI KUNIHIRO , NISHI KUNIHIKO , OTSUKA KENICHI
IPC分类号： H01L23/12 , H01L23/50
摘要： PURPOSE:To provide a BGA semiconductor device, which does not have defective electric connections even if a package is warped, a mounting substrate for the BGA semiconductor device and the mounting method thereof. CONSTITUTION:A semiconductor chip 3 is mounted on a substrate 1 having the circuit wiring. The electrodes of the semiconductor chip 3 and the circuit wirings are electrically connected. At least the semiconductor chip and the electric connecting part are sealed with resin 5. A plurality of solder bumps 8 are provided at the face on the opposite side of the face of the substrate 1, on which the semiconductor chip 3 is mounted. In this BGA semiconductor device, the central part of the substrate l is warped in the direction of the face 6 on the opposite side with respect to the face 2, on which the semiconductor chip 3 is mounted, in the protruding shape.

58. 发明专利

JPH06325109A SYSTEM AND METHOD FOR EVALUATING PRODUCT DESIGN SPECIFICATION 失效
公开(公告)号：JPH06325109A
公开(公告)日：1994-11-25
申请号：JP22905493
申请日：1993-09-14
申请人： HITACHI LTD
发明人： SUGINO KAZUHIRO , NISHIKAWA HIROKO , CHISAKI TAKAO , NISHI KUNIHIKO , YASUHARA TOSHIHIRO
IPC分类号： G06F17/50 , G06F19/00 , H01L21/02 , G06F15/60 , G06F15/20
摘要： PURPOSE:To generate relation among defective phenomena of past trial products, evaluation items at the time of an analysis of a product, and various elements of respective designs of the product and to evaluate and optimize a design specification plan for a new product on the basis of the relation. CONSTITUTION:A trial product data management part 24 has data including design specification defect information on existent trial products and a design knowledge management part 25 has respective analytic programs for the evaluation items. Feature quantities of a product shape and material are extracted from the design specification plan for the new product, data having feature quantities similar to the extracted feature quantities are take out of the trial product data management part 24, and a defect causal relation generation part 26 generates the relation (causal relation) among three elements, i.e., the defect phenomena, evaluation items, and various design elements. On the basis of the defect causal relation, an evaluation order generation part 28 generates the order of the evaluation items to be evaluated. In this order, the evaluation items are analyzed by a simulation program stored in the design knowledge management part 25 and a design plan evaluation part 42 decides whether or not the values of various design elements of the inputted product design specification plan need to be corrected on the basis of the analysis results.

59. 发明专利

JPH06163619A SEMICONDUCTOR DEVICE AND TRANFER MOLD DIE USED FOR ITS MANUFACTURE 失效
公开(公告)号：JPH06163619A
公开(公告)日：1994-06-10
申请号：JP31864992
申请日：1992-11-27
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： NISHIDA TAKAFUMI , ICHIHARA SEIICHI , ITO FUJIO , NISHI KUNIHIKO , SHIMOISHI TOMOAKI , YAMADA MASARU
IPC分类号： B29C45/02 , B29C45/26 , B29L31/34 , H01L21/56 , H01L23/50
摘要： PURPOSE:To prevent lead bent of a mold TCP and to eliminate formation of void of a package. CONSTITUTION:The tip of outer lead 9 is fixed by a guard ring 13 for protection, so lead bent is hard to take place. The guard ring is formed at the same time when a package is formed at transfer molding. The tip part of the flaw of a resin 37, having flown into the package cavity for forming the package, flows into, through a connection cavity, a flow cavity that forms the guard ring. In addition, the resin gradually flows into the flaw cavity also from a gate. The void generated by air entangled in the tip part of the resin flow comes out of the package cavity and comes into the flaw cavity. So, the void does not remain in a package 12.

60. 发明专利

JPH05102216A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05102216A
公开(公告)日：1993-04-23
申请号：JP26180791
申请日：1991-10-09
申请人： HITACHI LTD
发明人： YOSHIDA ISAMU , SAEKI JUNICHI , TSUNODA SHIGEHARU , NISHI KUNIHIKO
IPC分类号： H01L21/56
摘要： PURPOSE:To provide the technique with which a semiconductor element can be sealed in the state having no defects of molding such as shifting of an insert, penetrating void and the like. CONSTITUTION:A mold resin piece 5, which was molded in advance, is provided on the cavity part of the lower mold 2, a lead frame 3, on which a semiconductor element 4 is mounted, is formed, molded and the shifting of an insert can be suppressed.

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