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51. 发明授权

US5978869A Enhanced dual speed bus computer system 失效
标题翻译：增强型双速总线计算机系统
公开(公告)号：US5978869A
公开(公告)日：1999-11-02
申请号：US897573
申请日：1997-07-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1/08 , G06F13/42 , G06F1/12 , G06F13/00
CPC分类号： G06F13/4217 , G06F1/08
摘要： A methodology and implementing system 101 are provided in which a PCI bus is enhanced to operate at a plurality of data transfer speeds, including for example, 133 MHz in order to accommodate subsystem boards operating at higher frequencies, while at the same time allowing normal 66 MHz PCI clocking for devices designed to operate at the lower 66 MHz standard PCI speed. Master strobe MSTB 303, 403 and target strobe TSTB signals 309, 411 are generated in a handshaking methodology to determine if a master data transaction requesting device and a target data transaction device are designed to operate at the higher data transfer frequency. Higher frequency capable devices or boards are run at the increased frequency when both the requesting master and the selected target devices request the higher transfer rate, and standard devices or boards are run at the lower standard PCI frequency, while both master and target devices are coupled to and run from the same multi-speed PCI bus 125.
摘要翻译：提供了一种方法和实现系统101，其中PCI总线被增强以以多个数据传输速度操作，包括例如133MHz，以便容纳在较高频率下工作的子系统板，同时允许正常的66 设计用于在66 MHz标准PCI速度下运行的设备的MHz PCI时钟。在握手方法中产生主选通MSTB 303,403和目标选通TSTB信号309,411，以确定主数据交易请求装置和目标数据交易装置是否被设计为在较高数据传输频率下操作。当请求主机和所选择的目标设备请求更高的传输速率时，较高频率的设备或板以增加的频率运行，并且标准设备或板以较低的标准PCI频率运行，而主设备和目标设备都耦合从同一个多速PCI总线125运行并运行。

52. 发明授权

US5898888A Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system 失效
标题翻译：用于在计算机系统内跨多个PCI主机桥转换外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US5898888A
公开(公告)日：1999-04-27
申请号：US766737
申请日：1996-12-13
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/40
CPC分类号： G06F13/4036
摘要： A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges. A sequence of transactions is controlled through the two PCI host bridges to prevent a deadlock condition by not allowing a subsequent peer-to-peer write request destined for one of the two PCI local buses to be blocked from making progress through the two PCI host bridges.
摘要翻译：公开了一种用于在数据处理系统内跨多个外围组件互连（PCI）主机桥转换对等接入的方法和系统。根据本发明的方法和系统，处理器和系统存储器连接到系统总线。第一和至少第二PCI本地总线也分别经由第一PCI主机桥和第二PCI主机桥连接到系统总线。两个PCI本地总线具有与系统总线不同的总线事务协议。至少一个PCI设备连接到两个PCI本地总线中的每一个，并与处理器和系统存储器共享数据。此外，每个PCI设备与另一个PCI设备共享数据，作为跨多个PCI主机桥的对等设备。一系列事务通过两个PCI主机桥进行控制，以防止死锁状况不允许发往目的地为两个PCI本地总线之一的后续对等写入请求阻止通过两个PCI主机桥进行。

53. 发明申请

US20080005383A1 COMPUTER-IMPLEMENTED METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR STALLING DMA OPERATIONS DURING MEMORY MIGRATION 有权
标题翻译：计算机实现的方法，设备和计算机程序产品用于在存储器迁移期间进行DMA操作
公开(公告)号：US20080005383A1
公开(公告)日：2008-01-03
申请号：US11420236
申请日：2006-05-25
申请人： Carl Alfred Bender , Patrick Allen Buckland , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Carl Alfred Bender , Patrick Allen Buckland , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A computer-implemented method, apparatus, and computer program product are disclosed for migrating data from a source physical page to a destination physical page. A migration process is begun to migrate data from the source physical page to the destination physical page which causes a host bridge to enter a first state. The host bridge then suspends processing of direct memory access operations when the host bridge is in the first state. The data is migrated from the source physical page to the destination physical page while the host bridge is in the first state.
摘要翻译：公开了一种用于将数据从源物理页迁移到目的物理页的计算机实现的方法，装置和计算机程序产品。迁移过程开始将数据从源物理页面迁移到目标物理页面，导致主机桥接器进入第一个状态。然后，当主桥处于第一状态时，主机桥暂停对直接存储器访问操作的处理。当主桥处于第一状态时，数据将从源物理页迁移到目标物理页。

54. 发明授权

US07103789B2 Method, system, and product for indicating power status of field replaceable units 有权
标题翻译：用于指示现场可更换单元的电源状态的方法，系统和产品
公开(公告)号：US07103789B2
公开(公告)日：2006-09-05
申请号：US10755880
申请日：2004-01-13
申请人： George Henry Ahrens, Jr. , Steven Mark Thurber , Ronald Stanley Wesely
发明人： George Henry Ahrens, Jr. , Steven Mark Thurber , Ronald Stanley Wesely
IPC分类号： G06F1/26 , G06F1/28
CPC分类号： G06F1/30
摘要： A method, system, and product are disclosed for indicating a power status of multiple devices using hierarchically encoded indicators. Multiple nodes are included within a data processing system. Each node includes a different implementation of the devices. Each one of a first level of power indicators are associated with a different one of the nodes. Each one of a second level of power indicators is associated with a different one of the devices. A power status of each node is indicated utilizing one of the first level of power indicators. A power status of each device is indicated utilizing the second level of power indicators.
摘要翻译：公开了一种方法，系统和产品，用于使用分层编码的指示符指示多个设备的电力状态。数据处理系统中包含多个节点。每个节点包括不同的设备实现。第一级功率指示器中的每一个与不同的一个节点相关联。第二级功率指示器中的每一个与不同的设备相关联。使用第一级功率指示器之一来指示每个节点的电源状态。使用第二级电源指示灯指示每个设备的电源状态。

55. 发明授权

US06351784B1 System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction 有权
标题翻译：用于确定是否允许或必须允许后续交易或不允许绕过前一交易的系统
公开(公告)号：US06351784B1
公开(公告)日：2002-02-26
申请号：US09221930
申请日：1998-12-28
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/36
摘要： An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.
摘要翻译：实现了一种用于在数据处理系统中跨结构的中介交易序列的装置和方法。织物桥根据预定的协议订购前一事务和后续事务。使用协议确定后续事务是否可以绕过先前的事务，必须被允许绕过先前的事务，或不得允许绕过上一个事务。事务包括对系统内存的加载/存储（L / S）以及对系统内存事务的直接内存访问（DMA）。

56. 发明授权

US06347349B1 System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction 有权
标题翻译：用于确定是否允许或必须允许后续交易或不允许绕过前一交易的系统
公开(公告)号：US06347349B1
公开(公告)日：2002-02-12
申请号：US09221936
申请日：1998-12-28
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/4036
摘要： An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.
摘要翻译：实现了一种用于在数据处理系统中跨结构的中介交易序列的装置和方法。织物桥根据预定的协议订购前一事务和后续事务。使用协议确定后续事务是否可以绕过先前的事务，必须被允许绕过先前的事务，或不得允许绕过上一个事务。交易包括对输入/输出（I / O）设备的加载/存储（L / S）系统存储器和L / S以及对系统存储器和DMA对等交易的直接存储器访问（DMA）。

57. 发明授权

US06240474B1 Pipelined read transfers 失效
标题翻译：流水线读取传输
公开(公告)号：US06240474B1
公开(公告)日：2001-05-29
申请号：US08931705
申请日：1997-09-16
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/28 , G06F13/4027
摘要： A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request.
摘要翻译：提供了一种实现流水线读取传输或PRT的方法和实现系统。 PRT包括请求阶段和响应阶段。 PRT请求阶段涉及PRT请求主机传送到PRT请求目标，源地址，目的地地址和正在请求的数据的传输大小。在PRT响应阶段，PRT请求目标成为PRT响应主机，即PCI总线主机，并启动完成在发起PRT请求中请求的事务。

58. 发明授权

US06185642B2 Bus for high frequency operation with backward compatibility and hot-plug ability 失效
标题翻译：高性能PCI总线，用于高频操作，具有向后兼容性和热插拔能力
公开(公告)号：US06185642B2
公开(公告)日：2001-02-06
申请号：US09116058
申请日：1998-07-15
申请人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
摘要翻译：一种用于包括桥接器，外围总线和外围设备的计算机系统的外设互连，其中这些组件中的至少一个适于选择性地以高性能模式或低性能模式操作，高性能模式使用第一操作速度和第一协议，以及使用低于所述第一操作速度的第二操作速度的低性能模式，以及不同于第一协议的第二协议。所公开的实施例提供具有100MHz速度的高性能模式和不允许起搏的协议，以及使用66MHz或33MHz速度的低性能模式和允许起搏的标准PCI协议。高性能运行速度可以是低性能运行速度的两倍，通过在一个时钟沿将时钟频率和时钟数据加倍，或者在时钟信号的上升沿和下降沿同时处理数据，同时在较低的时钟时钟频率。高性能适配器可以提供拆分事务功能，具有支持拆分事务或别名拆分事务延迟事务的高性能网桥。也可以向后兼容性提供可选功能，如热插拔。

59. 发明授权

US06175888B1 Dual host bridge with peer to peer support 失效
标题翻译：双主机桥与对等支持
公开(公告)号：US06175888B1
公开(公告)日：2001-01-16
申请号：US08627810
申请日：1996-04-10
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/36 , G06F13/4027
摘要： A data processing system includes a processor, system memory and a number of peripheral devices, and one or more bridges which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus. The host bridge provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces in provided.
摘要翻译：数据处理系统包括处理器，系统存储器和多个外围设备以及可以在处理器，存储器和外围设备以及诸如网络中的其它主机或外围设备之间连接的一个或多个桥接器。诸如PCI主机桥的桥连接在主总线（例如系统总线）和辅助总线之间。主桥提供双主机桥功能，其创建两个辅助总线接口。这允许在一个双主机桥下增加负载能力，而在一个正常主桥下允许的较少数量的时隙。还包括附加的控制逻辑，用于提供仲裁控制和用于转向事务到适当的总线接口。另外，提供的两个辅助总线接口的对等支持。

60. 发明授权

US6134621A Variable slot configuration for multi-speed bus 失效
标题翻译：多速总线可变插槽配置
公开(公告)号：US6134621A
公开(公告)日：2000-10-17
申请号：US092153
申请日：1998-06-05
申请人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F13/14 , G06F13/40 , G06F13/00 , G06F1/08 , G06F13/38
CPC分类号： G06F13/4068
摘要： A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.
摘要翻译：提供了一种方法和装置，其中实现控制方案以使得PCI总线能够操作可以安装PCI设备的两个以上PCI插槽。检查PCI插槽以确定PCI设备是否安装在插槽中以及安装的PCI设备能够运行的速度。如果任何插槽中的任何一个插槽中都安装了一个33 MHz器件，则系统可以运行多于两个插槽，所有PCI设备将以33 MHz运行。当PCI插槽中没有安装33 MHz的卡或设备时，PCI设备仅安装在前两个插槽中，则系统只能以66 MHz的速度运行前两个插槽。在一个替代实施例中，默认配置例程将PCI总线速度设置为工作频率之一，并且如果在系统配置周期期间确定另一个速度更合适，则修改该默认值。

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