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51. 发明授权

US08711635B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08711635B2
公开(公告)日：2014-04-29
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译：非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压验证操作。

52. 发明授权

US08710573B2 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08710573B2
公开(公告)日：2014-04-29
申请号：US12831323
申请日：2010-07-07
申请人： Atsuhiro Kinoshita , Hiroshi Watanabe , Fumitaka Arai
发明人： Atsuhiro Kinoshita , Hiroshi Watanabe , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译：可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。

53. 发明申请

US20130010541A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130010541A1
公开(公告)日：2013-01-10
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

54. 发明申请

US20120037976A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20120037976A1
公开(公告)日：2012-02-16
申请号：US13235948
申请日：2011-09-19
申请人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
发明人： Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
IPC分类号： H01L27/105
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
摘要翻译：非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。

55. 发明申请

US20110272755A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110272755A1
公开(公告)日：2011-11-10
申请号：US13188803
申请日：2011-07-22
申请人： Masato ENDO , Fumitaka Arai
发明人： Masato ENDO , Fumitaka Arai
IPC分类号： H01L27/115
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source/drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source/drain regions formed on the surface of the semiconductor substrate.
摘要翻译：一种半导体器件，包括设置在单元晶体管区域中的半导体衬底上的第一绝缘膜，设置在第一绝缘膜上的第一导电膜，设置在第一导电膜上的电极间绝缘膜，设置在第一绝缘膜上的第二导电膜电极间绝缘膜，在其上表面具有第一金属硅化物膜，形成在所述半导体基板的表面上的第一源极/漏极区域，设置在所述半导体基板上的选择栅极晶体管中的至少一个中的第二绝缘膜区域和周边晶体管区域，第三导电膜，设置在第二绝缘膜上，并且具有厚度小于其顶表面上的第一金属硅化物膜的厚度的第二金属硅化物膜，以及第二源极/漏极区域形成在半导体基板的表面上。

56. 发明申请

US20110272745A1 SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20110272745A1
公开(公告)日：2011-11-10
申请号：US13185930
申请日：2011-07-19
申请人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L27/105
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

57. 发明申请

US20110250744A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110250744A1
公开(公告)日：2011-10-13
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

58. 发明申请

US20110249493A1 NAND FLASH MEMORY 失效
标题翻译： NAND闪存
公开(公告)号：US20110249493A1
公开(公告)日：2011-10-13
申请号：US13164486
申请日：2011-06-20
申请人： Atsuhiro SATO , Fumitaka Arai
发明人： Atsuhiro SATO , Fumitaka Arai
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

59. 发明授权

US07983086B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07983086B2
公开(公告)日：2011-07-19
申请号：US12564598
申请日：2009-09-22
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： G11C16/00
CPC分类号： G11C11/5628 , G11C16/0483
摘要： In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor.
摘要翻译：在第一和第二选择栅极晶体管被截止并且第一电压被施加到第二存储单元晶体管的控制栅极的状态下，第二存储单元晶体管连接到从存储器中选择的第一存储单元晶体管的源极线侧单元晶体管并且要被切断，高于第一电压的第二电压并且使得在存储单元晶体管导通时保持未选择的多个第三存储单元晶体管被施加到第三存储单元晶体管的控制栅极之后，通过向第一存储单元的控制栅极施加高于第二电压的第三电压，将第一存储单元晶体管的阈值电压改变为高于与擦除状态相对应的第一阈值电压的阈值电压晶体管。

60. 发明申请

US20110108905A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110108905A1
公开(公告)日：2011-05-12
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki ICHIGE , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

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