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51. 发明授权

US07397641B2 Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices 失效
标题翻译：用于改善ESD钳位装置的触发和振荡抑制的装置和方法
公开(公告)号：US07397641B2
公开(公告)日：2008-07-08
申请号：US11276411
申请日：2006-02-28
申请人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

52. 发明授权

US07253066B2 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US07253066B2
公开(公告)日：2007-08-07
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

53. 发明授权

US07085113B2 ESD protection power clamp for suppressing ESD events occurring on power supply terminals 失效
标题翻译： ESD保护电源钳位，用于抑制电源端子发生的ESD事件
公开(公告)号：US07085113B2
公开(公告)日：2006-08-01
申请号：US10711085
申请日：2004-08-20
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H01L27/0266
摘要： An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.
摘要翻译：用于抑制ESD事件的ESD保护电源钳。具有连接在集成电路的电源端子上的电源连接的钳位晶体管被连接以在ESD事件期间钳位电压。 RC定时电路定义用于触发FET导通的ESD电压的时间间隔。逆变器电路将RC和定时电路连接到钳位FET。动态反馈晶体管与逆变器和电源的一级串联连接。在ESD事件期间，反馈晶体管延迟了禁止FET晶体管的时间，提供了抵抗钳位晶体管失谐的增强的抗扰性，并迫使电路在雾触发器事件之后复位。

54. 发明授权

US06965503B2 Electro-static discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US06965503B2
公开(公告)日：2005-11-15
申请号：US10605441
申请日：2003-09-30
申请人： John Connor , Robert J. Gauthier, Jr. , Christopher S. Putnam , Alan L. Roberts
发明人： John Connor , Robert J. Gauthier, Jr. , Christopher S. Putnam , Alan L. Roberts
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).
摘要翻译：一种ESD保护电路，包括：一个或多个反相器（I 1，I 2，I 3），一个或多个反相器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT）与一个或多个逆变器（I 1，I 2，I 3）中的至少一个的输出端连接的夹持装置（N 3）; 以及与RC网络（11）的钳位装置（N 3）和输出节点（RCT）通信的反馈装置（NKP）。 RC网络可以包括一个或多个电阻器和一个或多个去耦电容器。在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I 1，I 2，I 3）中的每一个包括PFET和NFET对（P 0 / N 0，P 1 / N 1，P 2 / N 2）。

55. 发明授权

US06352905B1 Method and structure of high and low K buried oxide for SOI technology 失效
标题翻译：用于SOI技术的高K和低K埋氧体的方法和结构
公开(公告)号：US06352905B1
公开(公告)日：2002-03-05
申请号：US09702787
申请日：2000-11-01
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
IPC分类号： H01L2176
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译：用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体（第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

56. 发明授权

US6166420A Method and structure of high and low K buried oxide for SoI technology 失效
标题翻译：用于SoI技术的高K和低K埋氧体的方法和结构
公开(公告)号：US6166420A
公开(公告)日：2000-12-26
申请号：US526369
申请日：2000-03-16
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L27/12 , H01L29/786 , H01L29/00 , H01L23/58
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译：用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体（第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

57. 发明授权

US6100143A Method of making a depleted poly-silicon edged MOSFET structure 失效
标题翻译：制造耗尽多晶硅边缘MOSFET结构的方法
公开(公告)号：US6100143A
公开(公告)日：2000-08-08
申请号：US267239
申请日：1999-03-12
申请人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/762 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/6659 , H01L21/28105 , H01L21/28123 , H01L21/76224 , H01L29/4238 , H01L29/4983 , Y10S438/919
摘要： A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.
摘要翻译：具有减小的拐角设备问题的场效应晶体管包括形成在衬底中的源极和漏极区域，源极和漏极区域之间的沟道区域，邻近源极，沟道和漏极区域的衬底中的隔离区域; 以及在沟道区域上具有栅极掺杂剂并由栅极电介质分离的栅极。隔离区域定义了通道与隔离区域之间的接口的拐角区域。栅极包括耗尽栅极掺杂剂的区域，并且至少与沟道区域和隔离区域重叠，使得栅极导体层的耗尽部分之下的沟道拐角区域的电压阈值与角区域之间的沟道区域相比增加。 MOSFET栅极“拐角”上掺杂浓度降低的场效应晶体管具有改善的边缘电压容差。该结构具有改善的边缘电介质击穿和较低的MOSFET栅极引起的漏极泄漏（GIDL）。该结构适用于模拟应用，混合耐压电路和静电（ESD）网络。

58. 发明授权

US08987073B2 Self-protected metal-oxide-semiconductor field-effect transistor 有权
标题翻译：自保护金属氧化物半导体场效应晶体管
公开(公告)号：US08987073B2
公开(公告)日：2015-03-24
申请号：US13546509
申请日：2012-07-11
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/00 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/66
CPC分类号： H01L23/60 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
摘要翻译：金属氧化物半导体场效应晶体管的器件结构，设计结构和制造方法。栅极结构形成在衬底的顶表面上。第一和第二沟槽形成在与栅极结构的侧壁相邻的衬底中。第二沟槽横向形成在第一沟槽和第一侧壁之间。第一和第二外延层分别形成在第一和第二沟槽中。形成到作为漏极的第一外延层的接触。第二沟槽中的第二外延层不接触，使得第二外延层用作镇流电阻器。

59. 发明授权

US08796731B2 Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure 有权
标题翻译：低泄漏，低电容静电放电（ESD）硅控制背光（SCR），制造方法和设计结构
公开(公告)号：US08796731B2
公开(公告)日：2014-08-05
申请号：US12859801
申请日：2010-08-20
申请人： Michel J. Abou-Khalil , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： Michel J. Abou-Khalil , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H01L29/861
CPC分类号： H01L29/7412 , H01L27/0262
摘要： A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.
摘要翻译：提供了低泄漏，低电容二极管的触发静电放电（ESD）硅控整流器（SCR），制造方法和设计结构。该方法包括在绝缘体层上提供硅膜。该方法还包括形成从硅层的上侧延伸到绝缘体层的隔离区域。该方法还包括在硅层中形成一个或多个二极管，包括形成在由隔离区界定的阱中的p +区和n +区。隔离区域沿垂直方向隔离一个或多个二极管，并且绝缘体层在水平方向上将一个或多个二极管与下面的P或N型衬底隔离。

60. 发明授权

US08730624B2 Electrostatic discharge power clamp with a JFET based RC trigger circuit 有权
标题翻译：具有基于JFET的RC触发电路的静电放电电源钳位
公开(公告)号：US08730624B2
公开(公告)日：2014-05-20
申请号：US13076625
申请日：2011-03-31
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.
摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET）电阻器作为RC网络的电阻元件。

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