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51. 发明授权

US6051870A Process for fabricating semiconductor device including improved phosphorous-doped silicon dioxide dielectric film 失效
标题翻译：用于制造包括改进的磷掺杂二氧化硅介电膜的半导体器件的工艺
公开(公告)号：US6051870A
公开(公告)日：2000-04-18
申请号：US992333
申请日：1997-12-17
申请人： Minh Van Ngo
发明人： Minh Van Ngo
IPC分类号： H01L21/316 , H01L21/8247 , H01L29/00
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02274 , H01L21/31625
摘要： A semiconductor structure includes a substrate, a microelectronic device formed on the substrate, and a dielectric layer including silicon dioxide formed over the microelectronic device. The silicon dioxide layer is doped with phosphorous in the form of approximately 96% SiO.sub.2 and 4% phosphorous (PH.sub.3) by weight, and has high etch selectivity, polish rate and gettering capability as well as excellent step coverage. The present process also improves uniformity and process control because phosphine is a gas and does not have to be vaporized prior to deposition.
摘要翻译：半导体结构包括衬底，形成在衬底上的微电子器件，以及包含形成在微电子器件上的二氧化硅的电介质层。二氧化硅层以约96％SiO 2和4％磷（PH 3）的形式掺杂磷，并且具有高蚀刻选择性，抛光速率和吸杂能力以及优异的台阶覆盖。本方法还改善均匀性和工艺控制，因为磷化氢是气体，并且在沉积之前不必蒸发。

52. 发明授权

US09202758B1 Method for manufacturing a contact for a semiconductor component and related structure 有权
标题翻译：制造半导体元件用触点及其结构的方法
公开(公告)号：US09202758B1
公开(公告)日：2015-12-01
申请号：US11109965
申请日：2005-04-19
申请人： Paul R. Besser , Minh Van Ngo , Connie Pin-Chin Wang , Jinsong Yin , Hieu T. Pham
发明人： Paul R. Besser , Minh Van Ngo , Connie Pin-Chin Wang , Jinsong Yin , Hieu T. Pham
IPC分类号： H01L21/8234 , H01L29/49
CPC分类号： H01L21/823418 , H01L21/02129 , H01L21/02271 , H01L21/28556 , H01L21/28562 , H01L21/76801 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/485 , H01L23/53266 , H01L23/53295 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450° C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.
摘要翻译：适用于低温处理的半导体元件和半导体元件的制造方法。提供半导体衬底，并且使用原子层沉积（ALD）在半导体衬底上形成任选的氮化硅层。使用亚大气化学气相沉积（SACVD）在低于约450℃的温度下在氮化硅层上形成介电材料层。当不存在任选的氮化硅层时，SACVD介电材料形成在半导体衬底。通过SACVD介电层，通过氮化硅层形成具有侧壁的接触孔，并露出半导体衬底的一部分。在半导体衬底的暴露部分和接触孔的侧壁上形成氮化钨层。在氮化钨层上形成钨。

53. 发明授权

US08658496B2 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08658496B2
公开(公告)日：2014-02-25
申请号：US13617291
申请日：2012-09-14
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L21/336
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

54. 发明授权

US08564041B2 Contacts for semiconductor devices 有权
标题翻译：半导体器件的触点
公开(公告)号：US08564041B2
公开(公告)日：2013-10-22
申请号：US11551532
申请日：2006-10-20
申请人： Angela T. Hui , Wenmei Li , Minh Van Ngo , Amol Ramesh Joshi , Kuo-Tung Chang
发明人： Angela T. Hui , Wenmei Li , Minh Van Ngo , Amol Ramesh Joshi , Kuo-Tung Chang
IPC分类号： H01L27/108
CPC分类号： H01L29/78 , H01L27/115 , H01L27/11568
摘要： A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.
摘要翻译：存储器件包括多个存储单元和形成在存储单元上的电介质层。存储器件还包括形成在电介质层中的触点和邻近触头的侧表面形成的间隔件。间隔物可以抑制来自接触件的泄漏电流。

55. 发明授权

US07927723B1 Film stacks to prevent UV-induced device damage 有权
标题翻译：电影堆叠以防止紫外线引起的设备损坏
公开(公告)号：US07927723B1
公开(公告)日：2011-04-19
申请号：US11091524
申请日：2005-03-29
申请人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
发明人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
IPC分类号： G02B1/10 , G02B5/28 , B32B9/00 , B32B19/00
CPC分类号： G02B5/208
摘要： A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.
摘要翻译：膜堆叠包括在一个或多个器件上形成的层间电介质。薄膜叠层还包括形成在层间电介质上的具有高消光系数的第一层和形成在第一层上的具有低消光系数的第二层。第一层和第二层防止对一种或多种设备的紫外线诱发的损坏，同时最小化光刻工艺的反射率。

56. 发明授权

US07888269B2 Triple layer anti-reflective hard mask 有权
标题翻译：三层防反光硬面罩
公开(公告)号：US07888269B2
公开(公告)日：2011-02-15
申请号：US11256184
申请日：2005-10-24
申请人： Kouros Ghandehari , Hirokazu Tokuno , David Matsumoto , Christopher H. Raeder , Christopher Foster , Weidong Qian , Minh Van Ngo
发明人： Kouros Ghandehari , Hirokazu Tokuno , David Matsumoto , Christopher H. Raeder , Christopher Foster , Weidong Qian , Minh Van Ngo
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： G03F7/091 , H01L21/0276
摘要： A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.
摘要翻译：一种方法包括在半导体材料层上形成氮氧化硅（SiON），富硅氮化物（SiRN）或氮化硅（Si3N4）层。该方法还包括在SiON，SiRN或Si 3 N 4层上形成第一层抗反射材料，并在第一层上形成第二层抗反射材料。该方法还包括当蚀刻半导体材料层中的图案时，使用第一层，第二层和SiON，SiRN或Si3N4层作为掩模。

57. 发明授权

US07704878B2 Contact spacer formation using atomic layer deposition 有权
标题翻译：使用原子层沉积接触间隔物形成
公开(公告)号：US07704878B2
公开(公告)日：2010-04-27
申请号：US11240468
申请日：2005-10-03
申请人： Minh Van Ngo , Angela T. Hui , Amol Ramesh Joshi , Wenmei Li , Ning Cheng , Ankur Bhushan Agarwal , Norimitsu Takagi
发明人： Minh Van Ngo , Angela T. Hui , Amol Ramesh Joshi , Wenmei Li , Ning Cheng , Ankur Bhushan Agarwal , Norimitsu Takagi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.
摘要翻译：半导体器件中的接触结构包括介电材料层和通过介电材料形成的通孔。接触结构还包括通过使用原子层沉积（ALD）和沉积在通孔中的金属在通孔的侧壁上形成的间隔物。

58. 发明授权

US07323418B1 Etch-back process for capping a polymer memory device 有权
标题翻译：用于封盖聚合物存储器件的蚀刻工艺
公开(公告)号：US07323418B1
公开(公告)日：2008-01-29
申请号：US11102004
申请日：2005-04-08
申请人： Minh Van Ngo , Angela T. Hui , Sergey D. Lopatin
发明人： Minh Van Ngo , Angela T. Hui , Sergey D. Lopatin
IPC分类号： H01L21/302
CPC分类号： G11C13/0016 , G11C13/0014 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/1608 , H01L45/1683 , H01L51/0591
摘要： The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.
摘要翻译：本发明利用回蚀工艺来提供用于聚合物存储元件的电极帽。这允许聚合物存储元件形成在嵌入在衬底上形成的层中的通孔内。通过利用回蚀工艺，本发明提供了利用通孔的聚合物存储器件的适当功能所需的微小电触点。在本发明的一个实例中，在电介质层中形成一个或多个通孔以露出下层。然后在下层上的通孔内形成聚合物层，其中沉积在聚合物层上的顶部电极材料层填充通孔的剩余部分。然后通过蚀刻工艺去除顶部电极材料的多余部分以形成提供聚合物存储元件的电接触点的电极帽。

59. 发明授权

US07300886B1 Interlayer dielectric for charge loss improvement 有权
标题翻译：用于电荷损耗改善的层间电介质
公开(公告)号：US07300886B1
公开(公告)日：2007-11-27
申请号：US11147208
申请日：2005-06-08
申请人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
发明人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L27/115 , H01L27/11568
摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.
摘要翻译：一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。该方法还包括在高温下在控制栅极上沉积层间电介质。

60. 发明授权

US07060554B2 PECVD silicon-rich oxide layer for reduced UV charging 有权
标题翻译： PECVD富氧氧化物层，用于减少紫外线充电
公开(公告)号：US07060554B2
公开(公告)日：2006-06-13
申请号：US10617451
申请日：2003-07-11
申请人： Minh Van Ngo , Mark Ramsbey , Tazrien Kamal , Pei Yuan Gao
发明人： Minh Van Ngo , Mark Ramsbey , Tazrien Kamal , Pei Yuan Gao
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02274 , H01L21/31604 , H01L21/76829 , H01L21/76834 , H01L23/552 , H01L27/115 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.
摘要翻译：在金属化之前，通过PECVD在层间电介质上沉积具有减少的UV透射的富Si氧化硅层，从而减少V O。实施方案包括沉积具有1.7至2.0的R.I.的UV不透明的富Si氧化硅层。

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