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51. 发明申请

US20080092367A1 MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 失效
标题翻译：微孔MEMS器件及其制造方法
公开(公告)号：US20080092367A1
公开(公告)日：2008-04-24
申请号：US11968896
申请日：2008-01-03
申请人： Louis Hsu , Lawrence Clevenger , Timothy Dalton , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Louis Hsu , Lawrence Clevenger , Timothy Dalton , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01F41/04
CPC分类号： H01H50/005 , H01H2050/007 , Y10T29/4902 , Y10T29/49105 , Y10T29/49147
摘要： A method of fabricating a MEMS switch having a free moving inductive element within in micro-cavity guided by at least one inductive coil. The switch consists of an upper inductive coil at one end of a micro-cavity; optionally, a lower inductive coil; and a free-moving inductive element preferably made of magnetic material. The coils are provided with an inner permalloy core. Switching is achieved by passing a current through the upper coil, inducing a magnetic field unto the inductive element. The magnetic field attracts the free-moving inductive element upwards, shorting two open conductive wires, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the conductive wires open. When the chip is not mounted with the correct orientation, the lower coil pulls the free-moving inductive element back at its original position.
摘要翻译：一种制造具有由至少一个感应线圈引导的微腔内的自由运动的感应元件的MEMS开关的方法。开关由微腔一端的上感应线圈组成; 可选地，下感应线圈; 以及优选由磁性材料制成的自由移动的电感元件。线圈设有内坡道合金芯。通过使电流通过上部线圈，从而产生电感元件的磁场来实现切换。磁场向上吸引自由移动的感应元件，短路两根开放的导线，闭合开关。当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且导线打开。当芯片没有以正确的方向安装时，下线圈将自由移动的感应元件拉回其原始位置。

52. 发明申请

US20080020488A1 Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same 失效
标题翻译：具有高Q晶片背面电感器的半导体集成电路器件及其制造方法
公开(公告)号：US20080020488A1
公开(公告)日：2008-01-24
申请号：US11488242
申请日：2006-07-18
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。半导体衬底可以是SOI（绝缘体上硅）结构。

53. 发明申请

US20070190740A1 ENHANCED SILICON-ON-INSULATOR (SOI) TRANSISTORS AND METHODS OF MAKING ENHANCED SOI TRANSISTORS 审中-公开
标题翻译：增强型硅绝缘体（SOI）晶体管及其制造增强型SOI晶体管的方法
公开(公告)号：US20070190740A1
公开(公告)日：2007-08-16
申请号：US11733249
申请日：2007-04-10
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

54. 发明申请

US20070007665A1 STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS 有权
公开(公告)号：US20070007665A1
公开(公告)日：2007-01-11
申请号：US11160669
申请日：2005-07-05
申请人： Lawrence Clevenger , Mukta Farooq , Louis Hsu , William Landers , Donna Zupanski-Nielsen , Carl Radens , Chih-Chao Yang
发明人： Lawrence Clevenger , Mukta Farooq , Louis Hsu , William Landers , Donna Zupanski-Nielsen , Carl Radens , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/49 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/06102 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/49109 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , Y02P70/613 , H01L2224/29099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

55. 发明申请

US20060270098A1 Method to fabricate passive components using conductive polymer 审中-公开
公开(公告)号：US20060270098A1
公开(公告)日：2006-11-30
申请号：US11499364
申请日：2006-08-04
申请人： Lawrence Clevenger , Louis Hsu , Carl Radens , Li-Kong Wang , Kwong Wong
发明人： Lawrence Clevenger , Louis Hsu , Carl Radens , Li-Kong Wang , Kwong Wong
IPC分类号： H01L21/00 , H01L21/20 , H01L21/30
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

56. 发明申请

US20060249846A1 ELECTRICAL PROGRAMMABLE METAL RESISTOR 有权
标题翻译：电可编程金属电阻器
公开(公告)号：US20060249846A1
公开(公告)日：2006-11-09
申请号：US10908360
申请日：2005-05-09
申请人： Chih-Chao Yang , Lawrence Clevenger , James Demarest , Louis Hsu , Carl Radens
发明人： Chih-Chao Yang , Lawrence Clevenger , James Demarest , Louis Hsu , Carl Radens
IPC分类号： H01L23/52
CPC分类号： H01L23/5228 , H01L23/5256 , H01L23/5329 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.
摘要翻译：本发明提供一种电可编程金属电阻器及其制造方法，其中电迁移应力用于在结构中产生增加电阻器的电阻的空隙。具体而言，提供一种半导体结构，其包括包括至少一个电介质层的互连结构，其中所述至少一个电介质层包括至少两个导电区域和嵌入其中的覆盖互连区域，所述至少两个导电区域与所述覆盖互连区域由至少两个触点和至少所述互连区域通过扩散阻挡层与所述至少一个介电层分离，其中空隙存在于至少互连区域中，这增加了互连区域的电阻。

57. 发明授权

US07122898B1 Electrical programmable metal resistor 有权
标题翻译：电气可编程金属电阻
公开(公告)号：US07122898B1
公开(公告)日：2006-10-17
申请号：US10908360
申请日：2005-05-09
申请人： Chih-Chao Yang , Lawrence A. Clevenger , James J. Demarest , Louis C. Hsu , Carl Radens
发明人： Chih-Chao Yang , Lawrence A. Clevenger , James J. Demarest , Louis C. Hsu , Carl Radens
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5228 , H01L23/5256 , H01L23/5329 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.
摘要翻译：本发明提供一种电可编程金属电阻器及其制造方法，其中电迁移应力用于在结构中产生增加电阻器的电阻的空隙。具体而言，提供一种半导体结构，其包括包括至少一个电介质层的互连结构，其中所述至少一个电介质层包括至少两个导电区域和嵌入其中的覆盖互连区域，所述至少两个导电区域与所述覆盖互连区域由至少两个触点和至少所述互连区域通过扩散阻挡层与所述至少一个介电层分离，其中空隙存在于至少互连区域中，这增加了互连区域的电阻。

58. 发明申请

US20060202249A1 SIMPLIFIED BURIED PLATE STRUCTURE AND PROCESS FOR SEMICONDUCTOR-ON-INSULATOR CHIP 有权
标题翻译：半导体绝缘子芯片的简化平板结构和工艺
公开(公告)号：US20060202249A1
公开(公告)日：2006-09-14
申请号：US10906808
申请日：2005-03-08
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert Ho , Carl Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert Ho , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/10864 , H01L27/10867 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.
摘要翻译：本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单元半导体区域的至少一部分。掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

59. 发明申请

US20060163636A1 TRENCH CAPACITOR ARRAY HAVING WELL CONTACTING MERGED PLATE 失效
标题翻译： TRENCH电容阵列具有良好的接触合并板
公开(公告)号：US20060163636A1
公开(公告)日：2006-07-27
申请号：US10905808
申请日：2005-01-21
申请人： Kangguo Cheng , Babar Khan , Carl Radens
发明人： Kangguo Cheng , Babar Khan , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L29/945
摘要： According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.
摘要翻译：根据本发明的一个方面，提供了一种结构，其中沟槽电容器阵列包括与合并的掩埋板扩散区的阱接触。布置在基板中的阵列包括用于接收参考电位的触点。每个沟槽电容器包括形成在沟槽内的节点电介质和节点导体。掩埋板（BP）扩散从阵列的每个沟槽的下部横向向外延伸，BP扩散合并以在阵列上形成至少基本上连续的BP扩散区域。隔离区域在BP扩散区域的一部分上延伸。在衬底内形成掺杂阱区，该衬底从衬底的主表面延伸至低于基本上连续的BP扩散区的顶层的深度。还向阱区域提供电互连。

60. 发明申请

US20060160349A1 Interconnect structures with encasing cap and methods of making thereof 失效
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US20060160349A1
公开(公告)日：2006-07-20
申请号：US11034890
申请日：2005-01-14
申请人： Kwong Wong , Louis Hsu , Timothy Dalton , Carl Radens , Chih-Chao Yang , Lawrence Clevenger , Theodorus Standaert
发明人： Kwong Wong , Louis Hsu , Timothy Dalton , Carl Radens , Chih-Chao Yang , Lawrence Clevenger , Theodorus Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，包括：在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

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