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51. 发明授权

US08218371B2 Multi-bit flash memory device and method of analyzing flag cells of the same 有权
标题翻译：多位闪存器件及其分析标志单元的方法
公开(公告)号：US08218371B2
公开(公告)日：2012-07-10
申请号：US12467529
申请日：2009-05-18
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C2211/5646
摘要： Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination.
摘要翻译：公开了一种包括存储单元阵列和控制电路的多位闪存装置。存储单元阵列具有多个存储单元和多个标志单元。控制电路基于与标志单元的读取余量相对应的基准来确定标志单元是否被编程，并且响应于该确定来控制存储器单元的编程操作。

52. 发明授权

US07898871B2 Flash memory device operating at multiple speeds 有权
公开(公告)号：US07898871B2
公开(公告)日：2011-03-01
申请号：US11853958
申请日：2007-09-12
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/24
摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.

53. 发明授权

US07843758B2 Multi-chip package flash memory device and method for reading status data therefrom 有权
标题翻译：多芯片封装闪存器件和从其读取状态数据的方法
公开(公告)号：US07843758B2
公开(公告)日：2010-11-30
申请号：US11984595
申请日：2007-11-20
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C8/00
CPC分类号： G06F13/1684
摘要： A method for reading status data from a multi-chip memory device including pluralities of memory chips is comprised of: providing a command to request an output of the status data to the plurality of memory chips; and accepting the status data of the plurality of memory chips through multiple channels of the multi-chip memory device. The reading method of the status data is helpful to shortening a standby time for accepting the status data of the multi-chip memory device, enhancing an operation rate.
摘要翻译：一种用于从包括多个存储器芯片的多芯片存储器件读取状态数据的方法包括：向多个存储器芯片提供请求输出状态数据的命令; 以及通过多芯片存储器件的多个通道接受多个存储器芯片的状态数据。状态数据的读取方法有助于缩短用于接受多芯片存储器件的状态数据的待机时间，从而提高操作速率。

54. 发明申请

US20100259982A1 FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE 有权
标题翻译：闪速存储器件及其控制闪速存储器件的方法
公开(公告)号：US20100259982A1
公开(公告)日：2010-10-14
申请号：US12822246
申请日：2010-06-24
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C8/10 , G11C8/12 , G11C29/806 , G11C29/844
摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
摘要翻译：闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器，块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

55. 发明申请

US20090296472A1 FLASH MEMORY DEVICES AND METHODS OF PROGRAMMING THE SAME BY OVERLAPPING PROGRAMMING OPERATIONS FOR MULTIPLE MATS 有权
标题翻译：闪存存储器件及其编程方法通过重写多个程序的编程操作
公开(公告)号：US20090296472A1
公开(公告)日：2009-12-03
申请号：US12541429
申请日：2009-08-14
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译：通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。

56. 发明申请

US20070268751A1 Flash memory device and related high voltage generating circuit 有权
标题翻译：闪存器件及相关高压发生电路
公开(公告)号：US20070268751A1
公开(公告)日：2007-11-22
申请号：US11797989
申请日：2007-05-09
申请人： Dae-Seok Byeon , Hee-Won Lee
发明人： Dae-Seok Byeon , Hee-Won Lee
IPC分类号： G11C16/06 , G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/12
摘要： In a flash memory device, a high voltage generating circuit generates a high voltage and receives the high voltage as a switching voltage for controlling a voltage dividing circuit.
摘要翻译：在闪存装置中，高电压产生电路产生高电压并接收高电压作为用于控制分压电路的开关电压。

57. 发明申请

US20070146052A1 Charge pump 审中-公开
标题翻译：电荷泵
公开(公告)号：US20070146052A1
公开(公告)日：2007-06-28
申请号：US11489476
申请日：2006-07-20
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump is disclosed. The charge pump comprises a plurality of first voltage boosting circuits (VBCs), each comprising a first output node and a precharge circuit adapted to precharge the first output node, and at least one second VBC connected in series with the plurality of first VBCs, wherein each of the at least one second VBC does not comprise any precharge circuit.
摘要翻译：公开了电荷泵。电荷泵包括多个第一升压电路（VBC），每个包括第一输出节点和适于对第一输出节点预充电的预充电电路以及与多个第一VBC串联连接的至少一个第二VBC，其中所述至少一个第二VBC中的每一个不包括任何预充电电路。

58. 发明授权

US07190618B2 Semiconductor device for reducing coupling noise 有权
标题翻译：用于减少耦合噪声的半导体器件
公开(公告)号：US07190618B2
公开(公告)日：2007-03-13
申请号：US10915555
申请日：2004-08-11
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C16/26
摘要： Semiconductor devices, semiconductor memory device, or flash memories including a high voltage region including high voltage elements, a low voltage region including low voltage elements, and a switch transistor, such as a low voltage switch transistor, connecting the high voltage region and the high voltage region. The switch transistor reduces or eliminates coupling noise between sense nodes without increasing chip area.
摘要翻译：半导体器件，半导体存储器件或闪存，其包括包括高电压元件的高电压区域，包括低电压元件的低电压区域，以及连接高电压区域和高电压区域的诸如低压开关晶体管的开关晶体管电压区域。开关晶体管减少或消除感测节点之间的耦合噪声，而不增加芯片面积。

59. 发明授权

US07154789B2 High-voltage generator circuit and semiconductor memory device including the same 有权
标题翻译：高压发生器电路和包括其的半导体存储器件
公开(公告)号：US07154789B2
公开(公告)日：2006-12-26
申请号：US10977426
申请日：2004-10-28
申请人： Jong-Hwa Kim , Dae-Seok Byeon
发明人： Jong-Hwa Kim , Dae-Seok Byeon
IPC分类号： G11C5/14
CPC分类号： H02M3/073 , H02M2001/0041
摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.
摘要翻译：根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。分压器通过分压高电压在输出节点产生分压。放电部分响应于第一控制信号将高电压放电到电源电压。比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。

60. 发明申请

US20060274578A1 NAND flash memory device having page buffer adapted to discharge bit line voltage during erase operation 失效
标题翻译：具有适于在擦除操作期间放电位线电压的页缓冲器的NAND闪存器件
公开(公告)号：US20060274578A1
公开(公告)日：2006-12-07
申请号：US11443205
申请日：2006-05-31
申请人： Pan-Suk Kwak , Dae-Seok Byeon
发明人： Pan-Suk Kwak , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/16
摘要： A NAND flash memory device comprises a memory cell array comprising a plurality of memory cells, a plurality of page buffers, and an isolation circuit connected between the memory cell array and the plurality of page buffers. The isolation circuit comprises a high voltage transistor adapted to disconnect a first bit line connected to the memory cell array from a second bit line connected to the one of the page buffers during an erase operation of the NAND flash memory device. During the read operation, a third bit line arranged in parallel with the second bit line and connected to one of the page buffers is discharged to prevent the page buffer from being damaged due to coupling capacitance between the second and third bit lines.
摘要翻译： NAND闪速存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，多个页缓冲器以及连接在存储单元阵列与多个页缓冲器之间的隔离电路。隔离电路包括高电压晶体管，其适于在NAND闪速存储器件的擦除操作期间将连接到存储单元阵列的第一位线与连接到该页缓冲器之一的第二位线断开。在读取操作期间，放电与第二位线并联并连接到页面缓冲器之一的第三位线，以防止页缓冲器由于第二位线和第三位线之间的耦合电容而损坏。

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