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51. 发明申请

US20090164543A1 APPARATUS AND METHOD TO COMPUTE RECIPROCAL APPROXIMATIONS 失效
标题翻译：用于计算近似近似的装置和方法
公开(公告)号：US20090164543A1
公开(公告)日：2009-06-25
申请号：US11963833
申请日：2007-12-23
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/483
CPC分类号： G06F7/4873
摘要： A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.
摘要翻译：提出了一种用于减少存储相对近似值所需的存储器的方法和装置，如IEEE电气和电子工程师协会（IEEE）标准如IEEE 754所规定。互逆函数的单调属性用于约束值组。有效的比特向量用于表示组中的信息，导致非常紧凑的表格表示比存储表中的所有倒数近似的四倍小。

52. 发明授权

US07412584B2 Data alignment micro-architecture systems and methods 失效
标题翻译：数据对齐微架构系统和方法
公开(公告)号：US07412584B2
公开(公告)日：2008-08-12
申请号：US10838078
申请日：2004-05-03
申请人： Jose S. Niell , Gilbert M. Wolrich , Thomas L. Dmukauskas , Mark B. Rosenbluth
发明人： Jose S. Niell , Gilbert M. Wolrich , Thomas L. Dmukauskas , Mark B. Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3816 , G06F9/3842 , G06F12/04
摘要： Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.
摘要翻译：公开了用于在存储器访问和其他应用中对准数据的系统和方法。在一个实施例中，提供了一种系统，其包括存储器单元，移位器和可操作以将数据从存储器单元路由到移位器的控制逻辑，并向移位器发送数据要被移位的量的指示。在一个实施例中，控制逻辑提供对推测执行的支持。控制逻辑还可以允许大端和小端数据对准操作的复用，和/或数据对准操作与非数据对准操作的复用。在一个实施例中，存储器单元，移位器和控制逻辑集成在处理单元内，诸如网络处理器中的微引擎。

53. 发明申请

US20080162806A1 Storage Accelerator 有权
标题翻译：存储加速器
公开(公告)号：US20080162806A1
公开(公告)日：2008-07-03
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G06F12/06
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

54. 发明授权

US5418973A Digital computer system with cache controller coordinating both vector and scalar operations 失效
标题翻译：数字计算机系统与缓存控制器协调矢量和标量运算
公开(公告)号：US5418973A
公开(公告)日：1995-05-23
申请号：US902149
申请日：1992-06-22
申请人： James P. Ellis , Era Nangia , Nital Patwa , Bhavin Shah , Gilbert M. Wolrich
发明人： James P. Ellis , Era Nangia , Nital Patwa , Bhavin Shah , Gilbert M. Wolrich
IPC分类号： G06F9/38 , G06F15/78 , G06F15/80 , G06F9/34 , G06F13/00
CPC分类号： G06F15/8092 , G06F15/8069 , G06F9/30036 , G06F9/3834 , G06F9/3838
摘要： A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard. Preferably the cache controller includes vector logic which is responsive to vector information written in intra-processor registers by the execution unit. The vector logic keeps track of the vector length and blocks extra memory addresses generated by the execution unit for the vector elements. The vector logic also blocks the memory addresses of masked vector elements so that these addresses are not translated by the memory management unit.
摘要翻译：数字计算机系统包括标量CPU，向量处理器和共享高速缓冲存储器。标量CPU具有执行单元，存储器管理单元和高速缓存控制器单元。执行单元生成用于向量加载/存储指令的加载/存储存储器地址。加载/存储地址由存储器管理单元转换，并存储在也用于缓冲标量写入地址和写入数据的写入缓冲器中。高速缓存控制器协调 - 在向量处理器和共享缓存之间加载和存储标量读取和写入高速缓存。优选地，高速缓存控制器通过检查写入队列中的标量写入和向量加载/存储的冲突来允许在标量写入和向量加载/存储之前进行标量读取，并且还允许通过检查与向量的冲突来向量操作之前的向量加载/存储操作存储在向量注册记分牌中的信息。优选地，高速缓存控制器包括向量逻辑，其响应于由执行单元写入在处理器内的寄存器中的向量信息。矢量逻辑跟踪矢量长度，并阻止执行单元为矢量元素生成的额外的存储器地址。向量逻辑还阻塞被屏蔽向量元素的存储器地址，使得这些地址不被存储器管理单元转换。

55. 发明申请

US20170091120A1 Securing Writes to Memory Modules Having Memory Controllers 审中-公开
公开(公告)号：US20170091120A1
公开(公告)日：2017-03-30
申请号：US14865675
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/14 , G06F11/16 , G06F11/32
CPC分类号： G06F12/1408 , G06F11/1608 , G06F11/327 , G06F13/00 , G06F21/575 , G06F21/79 , G06F2212/1052
摘要： A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.

56. 发明授权

US09473168B1 Systems, methods, and apparatuses for compression using hardware and software 有权
标题翻译：使用硬件和软件进行压缩的系统，方法和装置
公开(公告)号：US09473168B1
公开(公告)日：2016-10-18
申请号：US14866746
申请日：2015-09-25
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Daniel F. Cutter
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： H03M7/00 , H03M7/30
CPC分类号： H03M7/3082 , H03M7/3086 , H03M7/40
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for compression using hardware and software. Embodiments include compressor hardware to operate on two streams with one of the streams being an offset of the other stream. Additionally, in some embodiments, the output of the compressor hardware is submitted to software for further processing.
摘要翻译：这里详细描述了使用硬件和软件进行压缩的系统，方法和装置的实施例。实施例包括在两个流之间操作的压缩器硬件，其中一个流是另一个流的偏移。另外，在一些实施例中，压缩机硬件的输出被提交给软件进行进一步的处理。

57. 发明授权

US09419792B2 Instruction for accelerating SNOW 3G wireless security algorithm 有权
标题翻译：加速SNOW 3G无线安全算法的指令
公开(公告)号：US09419792B2
公开(公告)日：2016-08-16
申请号：US13730216
申请日：2012-12-28
申请人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F15/00 , G06F7/00 , H04L9/06 , G09C1/00 , H04L29/06 , H04W12/02
CPC分类号： H04W12/02 , G06F9/30007 , G06F9/30036 , G06F9/30134 , G06F9/3887 , G09C1/00 , H04L9/065 , H04L9/0668 , H04L63/045 , H04L63/0457 , H04W12/04
摘要： Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.
摘要翻译：用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。

58. 发明授权

US09270698B2 Filter for network intrusion and virus detection 有权
标题翻译：过滤网络入侵和病毒检测
公开(公告)号：US09270698B2
公开(公告)日：2016-02-23
申请号：US12346734
申请日：2008-12-30
申请人： Vinodh Gopal , Christopher F. Clark , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Christopher F. Clark , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F11/00 , H04L29/06 , G06F7/02 , G06F21/56
CPC分类号： H04L63/145 , G06F7/02 , G06F17/30949 , G06F17/30985 , G06F21/567 , G06F2207/025 , H04L63/0245 , H04L63/1416
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
摘要翻译：公开了对网络包检测进行字符串匹配的方法和装置。在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配结果。

59. 发明授权

US09052985B2 Method and apparatus for efficient programmable cyclic redundancy check (CRC) 有权
标题翻译：用于高效可编程循环冗余校验（CRC）的方法和装置
公开(公告)号：US09052985B2
公开(公告)日：2015-06-09
申请号：US11963147
申请日：2007-12-21
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72 , H03M13/09
CPC分类号： G06F7/724 , G06F7/72 , H03M13/09
摘要： A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.
摘要翻译：一种在循环冗余校验（CRC）电路中优化多个还原级中的每一个以产生数据块的残差的方法和装置减少了用于执行减少的区域，同时通过多个阶段保持相同的延迟还原逻辑。在CRC减少电路中，Karatsuba算法，经典乘法和串行划分的混合混合结果导致平均面积减少了约20％，而关键路径延迟没有减少。

60. 发明授权

US08947270B2 Apparatus and method to accelerate compression and decompression operations 有权
标题翻译：加速压缩和减压操作的装置和方法
公开(公告)号：US08947270B2
公开(公告)日：2015-02-03
申请号：US13931877
申请日：2013-06-29
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich
IPC分类号： H03M7/00 , G06F9/30
CPC分类号： H03M7/3086 , G06F9/30145 , G06F9/30178
摘要： A processor is described that includes an instruction execution pipeline having an instruction fetch unit to fetch and decode an instruction. The processor also has an execution unit to execute the instruction. The execution unit has a state machine and content addressable memory (CAM) circuitry. The state machine is to receive a pointer to a stream of DEFLATE encoded information, fetch a section of the DEFLATE encoded information and apply the section of the DEFLATE encoded information to the CAM to obtain decoded DEFLATE information.
摘要翻译：描述了一种处理器，其包括具有用于获取和解码指令的指令获取单元的指令执行流水线。处理器还具有执行指令的执行单元。执行单元具有状态机和内容可寻址存储器（CAM）电路。状态机将接收指向DEFLATE编码信息流的指针，获取DEFLATE编码信息的一部分，并将DEFLATE编码信息的部分应用于CAM以获得解码的DEFLATE信息。

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