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51. 发明授权

US06150212A Shallow trench isolation method utilizing combination of spacer and fill 失效
标题翻译：使用间隔物和填充物的组合的浅沟槽隔离方法
公开(公告)号：US06150212A
公开(公告)日：2000-11-21
申请号：US359287
申请日：1999-07-22
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/762 , H01L21/8242
CPC分类号： H01L21/76232 , H01L27/10861 , H01L27/1087
摘要： A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
摘要翻译：一种用于在半导体衬底中形成隔离沟槽区域的方法包括：在半导体衬底中设置沟槽区域，至少在沟槽区域的侧壁上添加衬垫材料，并在其底表面处蚀刻沟槽区域，以将沟槽区域延伸到下面底面并形成缝隙区域。间隔物材料可以随后被加热，使得间隔物材料从侧壁流入缝隙区域。

52. 发明授权

US07256439B2 Trench capacitor array having well contacting merged plate 失效
标题翻译：具有良好接触的合并板的沟槽电容器阵列
公开(公告)号：US07256439B2
公开(公告)日：2007-08-14
申请号：US10905808
申请日：2005-01-21
申请人： Kangguo Cheng , Babar A. Khan , Carl J. Radens
发明人： Kangguo Cheng , Babar A. Khan , Carl J. Radens
IPC分类号： H01L31/119
CPC分类号： H01L29/945
摘要： According to an aspect of the invention, a structure is provided in which an array of trench capacitors includes a well contact to a merged buried plate diffusion region. The array, which is disposed in a substrate, includes a contact for receiving a reference potential. Each trench capacitor includes a node dielectric and a node conductor formed within the trench. Buried plate (BP) diffusions extend laterally outward from a lower portion of each trench of the array, the BP diffusions merging to form an at least substantially continuous BP diffusion region across the array. An isolation region extends over a portion of the BP diffusion region. A doped well region is formed within the substrate extending from a major surface of the substrate to a depth below a top level of the substantially continuous BP diffusion region. An electrical interconnection is also provided to the well region.
摘要翻译：根据本发明的一个方面，提供了一种结构，其中沟槽电容器阵列包括与合并的掩埋板扩散区的阱接触。布置在基板中的阵列包括用于接收参考电位的触点。每个沟槽电容器包括形成在沟槽内的节点电介质和节点导体。掩埋板（BP）扩散从阵列的每个沟槽的下部横向向外延伸，BP扩散合并以在阵列上形成至少基本上连续的BP扩散区域。隔离区域在BP扩散区域的一部分上延伸。在衬底内形成掺杂阱区，该衬底从衬底的主表面延伸至低于基本上连续的BP扩散区的顶层的深度。还向阱区域提供电互连。

53. 发明授权

US07084449B2 Microelectronic element having trench capacitors with different capacitance values 失效
标题翻译：具有不同电容值的沟槽电容器的微电子元件
公开(公告)号：US07084449B2
公开(公告)日：2006-08-01
申请号：US10710146
申请日：2004-06-22
申请人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
发明人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/66181 , H01L27/1087 , H01L27/10894 , H01L29/945
摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.
摘要翻译：提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处，并且第二电容器的顶部设置在距离主表面的第二深度处。

54. 发明授权

US08578305B2 Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure 有权
标题翻译：具有拉伸和/或压缩应变的半导体器件以及制造和设计结构的方法
公开(公告)号：US08578305B2
公开(公告)日：2013-11-05
申请号：US12984927
申请日：2011-01-05
申请人： Kangguo Cheng , Carl J. Radens
发明人： Kangguo Cheng , Carl J. Radens
IPC分类号： G06F17/50
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.
摘要翻译：具有施加拉伸和/或压缩应变的半导体器件及其制造半导体器件的方法和设计结构以增强通道应变。该方法包括为NFET和PFET形成栅极结构，并使用相同的沉积和蚀刻工艺在NFET和PFET的栅极结构上形成侧壁。该方法还包括在NFET和PFET的源极和漏极区域中提供应力材料。

55. 发明申请

US20110101378A1 SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE 有权
标题翻译：具有拉伸和/或压缩应变的半导体器件及其制造和设计结构的方法
公开(公告)号：US20110101378A1
公开(公告)日：2011-05-05
申请号：US12984927
申请日：2011-01-05
申请人： Kangguo Cheng , Carl J. Radens
发明人： Kangguo Cheng , Carl J. Radens
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.
摘要翻译：具有施加拉伸和/或压缩应变的半导体器件及其制造半导体器件的方法和设计结构以增强通道应变。该方法包括为NFET和PFET形成栅极结构，并使用相同的沉积和蚀刻工艺在NFET和PFET的栅极结构上形成侧壁。该方法还包括在NFET和PFET的源极和漏极区域中提供应力材料。

56. 发明授权

US08916933B2 Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure 有权
标题翻译：具有拉伸和/或压缩应变的半导体器件以及制造和设计结构的方法
公开(公告)号：US08916933B2
公开(公告)日：2014-12-23
申请号：US13491036
申请日：2012-06-07
申请人： Kangguo Cheng , Carl J. Radens
发明人： Kangguo Cheng , Carl J. Radens
IPC分类号： H01L21/70 , H01L29/66 , H01L29/78 , H01L21/8238 , H01L29/165
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The gate structures for an NFET and a PFET have identically formed sidewalls, and stress materials are provided in recesses in source and drain regions of the NFET and the PFET.
摘要翻译：具有施加拉伸和/或压缩应变的半导体器件及其制造半导体器件的方法和设计结构以增强通道应变。用于NFET和PFET的栅极结构具有相同形成的侧壁，并且应力材料设置在NFET和PFET的源极和漏极区域中的凹部中。

57. 发明授权

US07229877B2 Trench capacitor with hybrid surface orientation substrate 失效
标题翻译：具有混合表面取向衬底的沟槽电容器
公开(公告)号：US07229877B2
公开(公告)日：2007-06-12
申请号：US10904583
申请日：2004-11-17
申请人： Kangguo Cheng , Carl J. Radens
发明人： Kangguo Cheng , Carl J. Radens
IPC分类号： H01L21/8242
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0629 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L27/1207
摘要： Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.
摘要翻译：在具有混合表面取向的单个芯片上形成深沟槽电容器存储器件和逻辑器件的方法。该方法允许制造具有增强性能的片上系统（SoC），包括在（100）表面取向硅上的n型互补金属氧化物半导体（CMOS）器件SOI阵列和逻辑晶体管以及p型CMOS逻辑晶体管 on（110）表面取向硅。此外，该方法在混合表面取向SOI和体基板内制造硅衬底沟槽电容器。实现节省成本，其中阵列掩模开放和用于硅外延生长的图案化在相同的步骤和相同的掩模中完成。

58. 发明授权

US08802990B2 Self-aligned nano-scale device with parallel plate electrodes 有权
标题翻译：具有平行平板电极的自对准纳米级装置
公开(公告)号：US08802990B2
公开(公告)日：2014-08-12
申请号：US13432037
申请日：2012-03-28
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： H01B5/14 , H01L21/76 , H01L21/764
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

59. 发明授权

US08692649B2 Asset management infrastructure 有权
标题翻译：资产管理基础设施
公开(公告)号：US08692649B2
公开(公告)日：2014-04-08
申请号：US13296242
申请日：2011-11-15
申请人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
IPC分类号： H04Q9/00
CPC分类号： G08B13/14 , G06Q10/087
摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.
摘要翻译：用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。键码单元位于受保护的环境中，与资产管理区域有关。设备单元可以存储设备标识码。键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备如果设备移动到资产管理区域外，则单元从密钥单元接收。

60. 发明申请

US20130168395A1 SELF-LOCKING CONTAINER 有权
标题翻译：自锁式容器
公开(公告)号：US20130168395A1
公开(公告)日：2013-07-04
申请号：US13340776
申请日：2011-12-30
申请人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
发明人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
IPC分类号： B65D55/02 , B65D41/04
CPC分类号： B65D79/02 , A61J1/03 , A61J2200/72 , B65D41/04 , B65D55/10 , B65D2213/00
摘要： Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.
摘要翻译：提供自锁容器的方法和装置，以防止由于暴露于损害材料的有效性或安全性的条件而导致存储在容器中的材料的不期望的访问。容器可以是螺纹以接收带螺纹的盖子，并且容器可以包括螺栓，该螺栓可在通道内从缩回位置移动，该缩回位置允许盖子被螺纹连接或移除到锁定位置，从而防止盖子移除。螺栓通过驱动构件（例如双金属条或形状记忆元件）可移动到锁定位置，该双金属条或形状记忆元件响应于暴露于损害材料的状况而驱动螺栓。

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