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51. 发明授权

US07692460B2 Structure for precision integrated phase lock loop circuit loop filter 失效
标题翻译：精密集成锁相环电路环路滤波器结构
公开(公告)号：US07692460B2
公开(公告)日：2010-04-06
申请号：US12129514
申请日：2008-05-29
申请人： David William Boerstler , Jieming Qi
发明人： David William Boerstler , Jieming Qi
IPC分类号： H03L7/06
CPC分类号： H03H11/245
摘要： A design structure for a loop filter in a phase lock loop circuit comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.
摘要翻译：一种锁相环电路中的环路滤波器的设计结构，包括参考精密电阻器，第一和第二FET，其中第一FET的栅极连接到第二FET的栅极，以及连接到第一FET的滤波电容器用于产生电容器电压的FET。电容器电压施加到第一FET的源极，第二FET的源极和参考精密电阻的底部作为虚拟接地。由滤波电容产生的电容器电压设定第二FET的偏置点，使得第二FET包括集成精密电阻器的特性。将由第二FET产生的预定电压施加到第一FET的栅极，以设置第一FET的偏置点，使得第一FET包括集成精密电阻器的特性。

52. 发明申请

US20090108889A1 Precision Integrated Phase Lock Loop Circuit Loop Filter 有权
标题翻译：精密集成锁相环电路环路滤波器
公开(公告)号：US20090108889A1
公开(公告)日：2009-04-30
申请号：US11877710
申请日：2007-10-24
申请人： David William Boerstler , Jieming Qi
发明人： David William Boerstler , Jieming Qi
IPC分类号： H03L7/06
CPC分类号： H03H11/245
摘要： A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.
摘要翻译：一种锁相环电路中的环路滤波器，包括参考精密电阻器，第一FET和第二FET，其中第一FET的栅极连接到第二FET的栅极，以及连接到第一FET的滤波电容器，产生电容电压。电容器电压施加到第一FET的源极，第二FET的源极和作为虚拟接地的参考精密电阻的底部。由滤波电容产生的电容器电压设定第二FET的偏置点，使得第二FET包括集成精密电阻器的特性。将由第二FET产生的预定电压施加到第一FET的栅极，以设置第一FET的偏置点，使得第一FET包括集成精密电阻器的特性。

53. 发明申请

US20100164580A1 HIGH SPEED CLOCK SIGNAL DUTY CYCLE ADJUSTMENT 有权
标题翻译：高速时钟信号占空比调整
公开(公告)号：US20100164580A1
公开(公告)日：2010-07-01
申请号：US12347469
申请日：2008-12-31
申请人： David William Boerstler , Steven Mark Clements , Jieming Qi
发明人： David William Boerstler , Steven Mark Clements , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.
摘要翻译：时钟信号占空比调整电路包括占空比校正电路，其接收可能需要占空比校正的时钟输入信号。占空比校正电路可以从时钟输入信号导出第一和第二差分时钟信号。第一和第二差分时钟信号可以呈现相应的电压偏移。占空比校正电路包括电压偏移移位电路，其可以移位第一和第二差分时钟信号中的一个表现出的电压偏移，以调整时钟输出信号的有效占空比。占空比调整电路响应于占空比误差信号，从电压偏移调整的第一和第二差分时钟信号中导出时钟输出信号。

54. 发明申请

US20090108922A1 Method and System for Managing Voltage Swings Across Field Effect Transistors 失效
标题翻译：用于管理跨场效应晶体管的电压摆幅的方法和系统
公开(公告)号：US20090108922A1
公开(公告)日：2009-04-30
申请号：US12129506
申请日：2008-05-29
申请人： David William Boerstler , Jieming Qi
发明人： David William Boerstler , Jieming Qi
IPC分类号： G05F1/10
CPC分类号： H03H11/245
摘要： A circuit for managing voltage swings across FETs comprising a reference precision resistor, a first FET and a second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first FET and the third FET maintain a linear relationship with respective drain to source voltages of the first FET and the third FET.
摘要翻译：一种用于管理跨越FET的电压摆幅的电路，包括参考精密电阻器，第一FET和第二FET，其中第一FET的栅极连接到第二FET的栅极，其中第二FET的漏极 - 源极电阻为基本上等于或者是参考精密电阻器的电阻的倍数，并且其中第二FET的栅极电压被施加到第一FET的栅极以设置第一FET的偏置点，并且第三FET被级联到所述第一FET，其中所述第一FET的源极耦合到所述第三FET的漏极，以扩展其中所述第一FET和所述第三FET的相应栅极电压与所述第一FET的相应漏极至源极电压保持线性关系的电压范围第一FET和第三FET。

55. 发明授权

US07453293B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07453293B2
公开(公告)日：2008-11-18
申请号：US11467972
申请日：2006-08-29
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

56. 发明授权

US07318209B2 Pulse-width limited chip clock design 失效
标题翻译：脉宽限制芯片时钟设计
公开(公告)号：US07318209B2
公开(公告)日：2008-01-08
申请号：US10616881
申请日：2003-07-10
申请人： Anthony Gus Aipperspach , David William Boerstler , Dieter Wendel
发明人： Anthony Gus Aipperspach , David William Boerstler , Dieter Wendel
IPC分类号： G06F17/50
CPC分类号： H03K5/1565 , H03L7/06
摘要： A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.
摘要翻译：提供了一种用于限制电路的芯片时钟设计中的脉冲宽度的方法和装置。该电路接收具有时钟脉冲宽度的时钟信号。检测时钟信号的时钟脉冲宽度。确定时钟脉冲宽度是否大于最大时钟脉冲宽度。在确定时钟脉冲宽度大于最大时钟脉冲宽度的情况下，时钟信号的时钟脉冲宽度受到限制。

57. 发明授权

US07119587B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07119587B2
公开(公告)日：2006-10-10
申请号：US10850400
申请日：2004-05-20
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.
摘要翻译：本发明提供了状态校正。从触发器接收状态电路中的第一值。接收到的值被发送到第二触发器。如果出现错误状况，则第二触发器内的接收值被改变。接收到的值被发送到第三个触发器。一方面，发送到第三触发器的接收值包括未改变的接收值。在另一方面，发送到第三触发器的接收值包括发送改变的接收值。这允许状态机中的错误状态在几个时钟脉冲之后变为正确的状态。

58. 发明授权

US07061223B2 PLL manufacturing test apparatus 失效
标题翻译： PLL制造测试仪器
公开(公告)号：US07061223B2
公开(公告)日：2006-06-13
申请号：US10606580
申请日：2003-06-26
申请人： David William Boerstler , Kazuhiko Miki
发明人： David William Boerstler , Kazuhiko Miki
IPC分类号： G01R23/12 , H03L7/06 , H03B5/12
CPC分类号： G01R31/2824 , H03L7/06
摘要： A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.
摘要翻译：提供了一种用于测试锁相环（PLL）的方法和装置。将固定电平参考时钟信号和测试反馈时钟信号施加到PLL的相位频率检测器（PFD），以测量PLL的压控振荡器（VCO）的最小输出频率。将测试参考时钟信号和固定电平反馈时钟信号施加到PFD以测量VCO的最大输出频率。 PLL的锁定和捕获范围基于VCO的最大和最小频率来确定。

59. 发明授权

US06987824B1 Method and system for clock/data recovery for self-clocked high speed interconnects 失效
标题翻译：自定时高速互连的时钟/数据恢复方法和系统
公开(公告)号：US06987824B1
公开(公告)日：2006-01-17
申请号：US09666277
申请日：2000-09-21
申请人： David William Boerstler
发明人： David William Boerstler
IPC分类号： H04L7/02
CPC分类号： H04L7/0066 , H04L25/03878 , H04L25/061 , H04L25/4904
摘要： A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided. The asynchronous recovered non-return to zero signal is supplied to a data flip-flop along with the recovered clock out signal and a constant and the result is a synchronous recovered non-return to zero signal.
摘要翻译：提供了一种用于自定时高速互连的时钟/数据恢复的方法和系统。接收数据信号然后均衡。然后，均衡数据信号提供触发以分开“一”和“零”一次。均衡的曼彻斯特数据信号也被积分，与阈值相比较，以确定数据信号的负峰值和正峰值。然后在确定适当的峰值之后，将中位信号作为输入发送到设置复位触发器，由此输出异步恢复的不返回零信号。该异步恢复不返回到零信号，然后提供对“1”单稳态的使能输入，并且互补异步恢复不返回零信号向“零”单稳态提供使能输入。 “一”一次输出“一”时钟信号，“零”一次输出“零”时钟信号。验证这两个信号并提供恢复的时钟输出信号。异步恢复不返回零信号与恢复的时钟输出信号一起提供给数据触发器和常数，并且结果是同步恢复的不返回零信号。

60. 发明授权

US06522207B1 Apparatus and method for dynamic frequency adjustment in a frequency synthesizer 有权
标题翻译：频率合成器中动态频率调整的装置和方法
公开(公告)号：US06522207B1
公开(公告)日：2003-02-18
申请号：US09631720
申请日：2000-08-03
申请人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
发明人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
IPC分类号： H03L700
CPC分类号： H03L7/23 , G06F7/68 , H03L7/183
摘要： An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.
摘要翻译：一种用于在频率合成器中进行小频率调整的装置和方法。频率合成器包括通过固定分频器的反馈的锁相环的前向部分和连接到动态可变分频器的锁相环的前部的输出。通过改变可变分频器中的分频常数，分频器的输出可以以小的增量快速变化。动态可变分频器是本设计的关键。该数字电路存储当前除数值，并具有新的除数值的输入。当发送信号以切换到新的除数值时，电路使用增量器和相关联的逻辑来快速变化到新的除法常数。

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