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51. 发明授权

US07220312B2 Methods for treating semiconductor substrates 有权
标题翻译：半导体衬底处理方法
公开(公告)号：US07220312B2
公开(公告)日：2007-05-22
申请号：US10099216
申请日：2002-03-13
申请人： Trung Tri Doan , Lyle D. Breiner , Er-Xuan Ping , Lingyi A. Zheng
发明人： Trung Tri Doan , Lyle D. Breiner , Er-Xuan Ping , Lingyi A. Zheng
IPC分类号： C30B23/00
CPC分类号： H01L21/0228 , C23C16/0236 , C23C16/0245 , C23C16/45546 , C23C16/54 , C30B25/02 , H01L21/02046 , H01L21/0214 , H01L21/02142 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/02211 , H01L21/02326 , H01L21/28562 , H01L21/3144 , H01L21/31604 , H01L21/31683 , H01L21/3185 , H01L21/76841 , H01L21/76856 , H01L21/76888
摘要： The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.
摘要翻译：本发明包括用于处理多个分立半导体衬底的方法。离散的半导体衬底被放置在反应室内。当衬底在室内时，它们同时暴露于H，F和Cl中的一种或多种以除去天然氧化物。在除去天然氧化物之后，将基板同时暴露于第一反应性材料，以在基底的至少一些暴露表面上形成第一质量。将第一反应性材料从反应室中除去，随后将基板暴露于第二反应性材料以将第一质量转化为第二质量。本发明还包括可以用于多个分立半导体衬底的同时ALD处理的装置。

52. 发明授权

US07148118B2 Methods of forming metal nitride, and methods of forming capacitor constructions 有权
标题翻译：形成金属氮化物的方法，以及形成电容器结构的方法
公开(公告)号：US07148118B2
公开(公告)日：2006-12-12
申请号：US10887962
申请日：2004-07-08
申请人： Lingyi A. Zheng , Er-Xuan Ping
发明人： Lingyi A. Zheng , Er-Xuan Ping
IPC分类号： H01L21/20
CPC分类号： H01L21/02175 , C23C16/34 , H01L21/022 , H01L21/02205 , H01L21/3141 , H01L21/76841 , H01L28/60
摘要： The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion of the metal nitride further from the dielectric material is formed from a halogenated metal-containing precursor. The methodology of the present invention can be utilized for forming capacitor constructions, with the portion of the metal nitride formed from the halogenated metal-containing precursor being incorporated into a capacitor electrode.
摘要翻译：本发明包括在电介质材料附近形成金属氮化物的方法。金属氮化物包括两部分，其中一个部分比另一部分更接近电介质材料。最接近介电材料的金属氮化物的部分由非卤化的含金属的前体形成，并且来自电介质材料的金属氮化物的部分由含卤化金属的前体形成。本发明的方法可以用于形成电容器结构，其中由含卤化金属的前体形成的金属氮化物的一部分被并入电容器电极中。

53. 发明授权

US07112544B2 Method of atomic layer deposition on plural semiconductor substrates simultaneously 有权
标题翻译：同时在多个半导体衬底上沉积原子层的方法
公开(公告)号：US07112544B2
公开(公告)日：2006-09-26
申请号：US10846425
申请日：2004-05-13
申请人： Trung Tri Doan , Lyle D. Breiner , Er-Xuan Ping , Lingyi A. Zheng
发明人： Trung Tri Doan , Lyle D. Breiner , Er-Xuan Ping , Lingyi A. Zheng
IPC分类号： H01L21/44
CPC分类号： H01L21/0228 , C23C16/0236 , C23C16/0245 , C23C16/45546 , C23C16/54 , C30B25/02 , H01L21/02046 , H01L21/0214 , H01L21/02142 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/02211 , H01L21/02326 , H01L21/28562 , H01L21/3144 , H01L21/31604 , H01L21/31683 , H01L21/3185 , H01L21/76841 , H01L21/76856 , H01L21/76888
摘要： The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.
摘要翻译：本发明包括用于处理多个分立半导体衬底的方法。离散的半导体衬底被放置在反应室内。当衬底在室内时，它们同时暴露于H，F和Cl中的一种或多种以除去天然氧化物。在除去天然氧化物之后，将基板同时暴露于第一反应性材料，以在基底的至少一些暴露表面上形成第一质量。将第一反应性材料从反应室中除去，随后将基板暴露于第二反应性材料以将第一质量转化为第二质量。本发明还包括可以用于多个分立半导体衬底的同时ALD处理的装置。

54. 发明授权

US07034353B2 Methods for enhancing capacitors having roughened features to increase charge-storage capacity 失效
公开(公告)号：US07034353B2
公开(公告)日：2006-04-25
申请号：US09965240
申请日：2001-09-26
申请人： Randhir P. S. Thakur , Garry A. Mercaldi , Michael Nuttall , Shenlin Chen , Er-Xuan Ping
发明人： Randhir P. S. Thakur , Garry A. Mercaldi , Michael Nuttall , Shenlin Chen , Er-Xuan Ping
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C11/404 , G11C17/16 , H01L21/28568 , H01L21/76888 , H01L27/1085 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/60 , H01L28/82 , H01L28/84
摘要： Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

55. 发明授权

US07023039B2 Capacitor structures with dual-sided electrode 失效
标题翻译：具有双面电极的电容结构
公开(公告)号：US07023039B2
公开(公告)日：2006-04-04
申请号：US10234562
申请日：2002-09-03
申请人： Shenlin Chen , Er-Xuan Ping
发明人： Shenlin Chen , Er-Xuan Ping
IPC分类号： H01L27/108
CPC分类号： H01L28/84 , H01L27/0805 , H01L27/10852 , H01L27/10855 , H01L28/91 , Y10S438/964
摘要： The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies, and capacitor structures.
摘要翻译：本发明包括形成电容器电极的方法。提供牺牲材料侧壁以至少部分地围绕开口延伸。在开口内形成第一含硅材料以部分地填充开口，并且掺杂有导电性增强掺杂剂。第二含硅材料形成在部分填充的开口内，并且被提供为比第一含硅材料低掺杂导电性增强掺杂剂。第二含硅材料中的至少一些被转换成半球形晶粒硅，并且去除至少一些牺牲材料侧壁。本发明还包括形成具有上述电容器电极的电容器和电容器组件的方法。此外，本发明包括电容器组件和电容器结构。

56. 发明申请

US20060019475A1 Method of depositing polysilicon 审中-公开
标题翻译：沉积多晶硅的方法
公开(公告)号：US20060019475A1
公开(公告)日：2006-01-26
申请号：US11234334
申请日：2005-09-23
申请人： Michael Nuttall , Er-Xuan Ping , Yongjun Hu
发明人： Michael Nuttall , Er-Xuan Ping , Yongjun Hu
IPC分类号： H01L21/20
CPC分类号： H01L21/28525 , C23C16/04 , C23C16/24 , H01L21/28562 , H01L21/31604 , H01L21/32051 , H01L21/76879 , H01L28/60 , H01L29/41775 , H01L29/41783 , H01L29/7834
摘要： A method of depositing polysilicon includes positioning a substrate within a chemical vapor deposition reactor. The substrate has an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor to provide a reactive atmosphere under conditions effective to substantially selectively deposit polysilicon on the crystalline region relative to the amorphous region. The reactive atmosphere during the depositing consists essentially of a gaseous silane precursor.
摘要翻译：沉积多晶硅的方法包括将衬底定位在化学气相沉积反应器内。衬底具有暴露的基本上结晶的区域和暴露的基本无定形区域。包含硅的气态前体被供给到化学气相沉积反应器，以在有效地相对于非晶区域在晶体区域上基本上选择性地沉积多晶硅的条件下提供反应性气氛。沉积期间的反应性气氛基本上由气态硅烷前体组成。

57. 发明申请

US20060019442A1 Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US20060019442A1
公开(公告)日：2006-01-26
申请号：US11234328
申请日：2005-09-23
申请人： Michael Nuttall , Er-Xuan Ping , Yongjun Hu
发明人： Michael Nuttall , Er-Xuan Ping , Yongjun Hu
IPC分类号： H01L21/8242
CPC分类号： H01L21/28525 , C23C16/04 , C23C16/24 , H01L21/28562 , H01L21/31604 , H01L21/32051 , H01L21/76879 , H01L28/60 , H01L29/41775 , H01L29/41783 , H01L29/7834
摘要： A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed substantially amorphous material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric layer relative to the exposed substantially amorphous material, and the polysilicon is formed into a second capacitor electrode.
摘要翻译：形成电容器的方法包括在衬底上形成第一电容器电极。在第一电容器电极上形成基本上结晶的电容器电介质层。具有基本上结晶的电容器电介质层的衬底设置在化学气相沉积反应器内。这种衬底具有暴露的基本无定形的材料。包含硅的气态前体在有效基本上选择性地在基本上结晶的电容器电介质层上沉积多晶硅相对于暴露的基本无定形材料的条件下被馈送到化学气相沉积反应器，并且多晶硅形成第二电容器电极。

58. 发明授权

US06977407B2 Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth 失效
标题翻译：硅和氧化物表面之间的均匀成核对于薄氮化硅膜生长
公开(公告)号：US06977407B2
公开(公告)日：2005-12-20
申请号：US10732962
申请日：2003-12-11
申请人： Er-Xuan Ping
发明人： Er-Xuan Ping
IPC分类号： H01L21/02 , H01L21/20 , H01L21/318 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L21/3185 , H01L27/10817 , H01L28/75 , H01L28/84 , H01L28/90 , H01L28/91
摘要： A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.
摘要翻译：在硅和氧化物表面之间提供均匀成核的方法，用于生长半导体器件中使用的均匀薄的氮化硅层。首先，在具有氮化接受和电阻材料的半导体组件上形成非导电氮化物成核增强单层。为了本发明的目的，氮化物成核增强单层是容易接受氮原子结合到材料本身的材料。接下来，在非导电氮化物成核增强单层上形成氮化硅层。非导电氮化物成核增强单层在氮化接触材料和用于氮化硅的氮化电阻材料两者上均匀成核，从而允许生长均匀的氮化物薄层。

59. 发明授权

US06972223B2 Use of atomic oxygen process for improved barrier layer 失效
标题翻译：使用原子氧工艺改善阻挡层
公开(公告)号：US06972223B2
公开(公告)日：2005-12-06
申请号：US09805911
申请日：2001-03-15
申请人： Ronald A. Weimer , Er-Xuan Ping
发明人： Ronald A. Weimer , Er-Xuan Ping
IPC分类号： H01L21/314 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L23/31 , H01L27/108 , H01L21/8238
CPC分类号： H01L21/823475 , H01L21/3145 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/823425 , H01L23/3192 , H01L27/10811 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.
摘要翻译：公开了一种在玻璃膜和存储器件的有源区之间形成的复合阻挡层。复合阻挡层包括通过原子沉积工艺形成的氧化物层和形成在氧化物层上的绝缘层，例如氮化物阻挡层。复合阻挡层消除了杂质原子从玻璃膜扩散到器件的有源区中。

60. 发明授权

US06919638B2 Method, structure and process flow to reduce line-line capacitance with low-K material 有权
标题翻译：方法，结构和工艺流程，以低K材料降低线路电容
公开(公告)号：US06919638B2
公开(公告)日：2005-07-19
申请号：US10625952
申请日：2003-07-23
申请人： Ying Huang , Er-Xuan Ping
发明人： Ying Huang , Er-Xuan Ping
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/04
CPC分类号： H01L21/76844 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76852 , H01L21/76885 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.
摘要翻译：提供了使用低介电常数（K）材料降低线路电容的改进方法，结构和工艺流程。根据本发明的实施例形成具有单级互连的半导体器件的结构以及具有多个互连级别的半导体器件。在本发明的实施例中，形成具有覆盖有标准K材料的第一低K材料的初始电介质结构。在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。具有多层导电互连的本发明的实施例通过采用类似于用于形成第一级导电布线和介于其之间的介电材料的方法和材料而形成。本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

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