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51. 发明申请

US20080191809A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
公开(公告)号：US20080191809A1
公开(公告)日：2008-08-14
申请号：US12098483
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

52. 发明申请

US20080174345A1 METHOD AND APPARATUS FOR MEASURING THE DUTY CYCLE OF A DIGITAL SIGNAL 有权
标题翻译：用于测量数字信号占空比的方法和装置
公开(公告)号：US20080174345A1
公开(公告)日：2008-07-24
申请号：US11931879
申请日：2007-10-31
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K21/16
CPC分类号： G01R29/02 , G01R31/31725 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
摘要翻译：所公开的方法和装置测量时钟信号的占空比。可变占空比电路从时钟信号发生器接收时钟信号。可变占空比电路根据其接收到的占空比指数值来调整时钟信号的占空比。可变占空比电路将占空比调整的时钟信号提供给分频器电路。该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。然后，该装置从最大频率确定占空比调整的时钟信号的占空比。

53. 发明授权

US07358785B2 Apparatus and method for extracting a maximum pulse width of a pulse width limiter 失效
标题翻译：一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法
公开(公告)号：US07358785B2
公开(公告)日：2008-04-15
申请号：US11278842
申请日：2006-04-06
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。第11 / 109,090号（以下简称“090”）。在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

54. 发明授权

US07350095B2 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US07350095B2
公开(公告)日：2008-03-25
申请号：US11082973
申请日：2005-03-17
申请人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/00 , G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

55. 发明申请

US20080012617A1 Duty Cycle Correction Circuit Whose Operation is Largely Independent of Operating Voltage and Process 有权
公开(公告)号：US20080012617A1
公开(公告)日：2008-01-17
申请号：US11457637
申请日：2006-07-14
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

56. 发明授权

US07245161B2 Apparatus and method for verifying glitch-free operation of a multiplexer 失效
标题翻译：用于验证多路复用器的无毛刺操作的装置和方法
公开(公告)号：US07245161B2
公开(公告)日：2007-07-17
申请号：US11227026
申请日：2005-09-15
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K17/00
CPC分类号： G01R31/31708 , G01R31/31725
摘要： An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.
摘要翻译：提供一种用于验证多路复用器无毛刺操作的装置和方法。该装置包括具有多个触发器元件的电路，多个触发器元件接收作为多路复用器的输入的多个时钟信号作为输入，以及基于对解码器的控制输入生成的解码器的对应的同步输出信号。来自解码器的同步输出信号被用作到多个触发器的触发信号。触发器根据触发信号对时钟信号进行采样，并向逻辑门提供输出。逻辑门对来自触发器的输出进行操作，以产生指示无毛刺操作被验证或未被验证的输出信号。

57. 发明授权

US07132896B2 Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs) 有权
标题翻译：用于最小化锁相环（PPL）中的滤波电容泄漏引起的抖动的电路
公开(公告)号：US07132896B2
公开(公告)日：2006-11-07
申请号：US10981155
申请日：2004-11-04
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L7/093 , H03L7/095 , H03B1/04
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/095
摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.
摘要翻译：提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。

58. 发明授权

US07113881B2 Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment 失效
标题翻译：在制造环境中半自动提取和监控二极管理想的方法和装置
公开(公告)号：US07113881B2
公开(公告)日：2006-09-26
申请号：US10981157
申请日：2004-11-04
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R27/28 , G01R31/26
CPC分类号： G01R31/2632
摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.
摘要翻译：提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

59. 发明授权

US08381143B2 Structure for a duty cycle correction circuit 失效
标题翻译：占空比校正电路的结构
公开(公告)号：US08381143B2
公开(公告)日：2013-02-19
申请号：US13014828
申请日：2011-01-27
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00221
摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要翻译：提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时，输入信号通过线性电阻器路由。线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

60. 发明授权

US07786813B2 Interleaved voltage controlled oscillator 有权
公开(公告)号：US07786813B2
公开(公告)日：2010-08-31
申请号：US12098490
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

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