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51. 发明授权

US07156925B1 Using supercritical fluids to clean lenses and monitor defects 有权
标题翻译：使用超临界流体清洁镜头并监测缺陷
公开(公告)号：US07156925B1
公开(公告)日：2007-01-02
申请号：US10978844
申请日：2004-11-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan , Srikanteswara Dakshina-Murthy
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan , Srikanteswara Dakshina-Murthy
IPC分类号： G03B27/42
CPC分类号： G03F7/2041 , G03F7/70341 , G03F7/70925
摘要： Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.
摘要翻译：公开了浸没式光刻方法，包括通过透镜和浸没液体照射第一光致抗蚀剂，浸没液体在第一装置中与透镜和第一光致抗蚀剂接触; 在第二装置中使透镜与超临界流体接触; 以及通过所述透镜和浸没液体照射第二光致抗蚀剂，所述浸没液体与所述透镜和所述第二光致抗蚀剂接触。

52. 发明授权

US07065427B1 Optical monitoring and control of two layers of liquid immersion media 失效
标题翻译：两层液浸介质的光学监测与控制
公开(公告)号：US07065427B1
公开(公告)日：2006-06-20
申请号：US10979367
申请日：2004-11-01
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan
IPC分类号： G06F19/00 , G02B7/00 , H01L21/00
CPC分类号： G03F7/7085 , G03F7/70341 , G03F7/70591
摘要： A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.
摘要翻译：用于光刻工艺的多层浸渍介质监测系统监测半导体制造工艺的浸渍介质的特性。多层浸渍介质至少包括第一密度（或粘度）的第一液体和较低密度（或粘度）的第二液体，它们都分散在最终的光学部件和半导体层之间。提供更高密度的层以在光刻过程中减少浸没介质中的湍流。散射测量系统监测多层浸没介质的光学特性，以实现光刻工艺的控制。

53. 发明申请

US20060121711A1 Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions 失效
标题翻译：用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法
公开(公告)号：US20060121711A1
公开(公告)日：2006-06-08
申请号：US11002586
申请日：2004-12-03
申请人： Mark Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
发明人： Mark Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/32139 , H01L29/66628 , H01L29/66659
摘要： A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
摘要翻译：在多晶硅栅电极上形成特定尺寸的间隔物的方法在选择性外延生长期间保护多晶硅栅电极的侧壁。无论是不对称的还是对称的，通过在限定多晶硅栅电极图案和图案中使用相同的特定曝光工具（例如193nm波长步长和扫描曝光工具）和相同的图案掩模版来精确限定间隔件，同时采用紧密对准规格。

54. 发明申请

US20050146059A1 Method for forming rectangular-shaped spacers for semiconductor devices 有权
标题翻译：用于形成用于半导体器件的矩形间隔件的方法
公开(公告)号：US20050146059A1
公开(公告)日：2005-07-07
申请号：US10747680
申请日：2003-12-30
申请人： Huicai Zhong , Srikanteswara Dakshina-Murthy
发明人： Huicai Zhong , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/266 , H01L21/336 , H01L27/088
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/6656
摘要： A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.
摘要翻译：半导体器件及其制造方法通过在衬底和栅电极上沉积间隔层形成间隔物并在间隔层上形成保护层。干蚀刻保护层以在间隔层上留下薄膜侧壁。然后蚀刻间隔层，其中保护层保护间隔层的外侧壁。该蚀刻在栅极上产生具有平行于栅电极侧壁延伸的基本垂直侧壁的间隔物。间隔物的I形形状在源/漏离子注入过程中防止穿通，从而提供改进的源极/漏极注入剂量分布。

55. 发明申请

US20050020019A1 Method for semiconductor gate line dimension reduction 有权
标题翻译：半导体栅极线尺寸减小的方法
公开(公告)号：US20050020019A1
公开(公告)日：2005-01-27
申请号：US10922093
申请日：2004-08-19
申请人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
发明人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L21/3205
CPC分类号： H01L29/66477 , H01L21/28123 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
摘要翻译：为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。所得到的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

56. 发明授权

US07405032B1 Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction 有权
标题翻译：非平版收缩技术和修剪过程的组合，用于栅极形成和线边缘粗糙度降低
公开(公告)号：US07405032B1
公开(公告)日：2008-07-29
申请号：US10645364
申请日：2003-08-21
申请人： Gilles Amblard , Srikanteswara Dakshina-Murthy , Bhanwar Singh
发明人： Gilles Amblard , Srikanteswara Dakshina-Murthy , Bhanwar Singh
IPC分类号： G01B11/30 , G01B11/00 , G03C5/00
CPC分类号： G01B11/30 , G03F7/40
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit.Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.
摘要翻译：本发明一般涉及光刻系统和方法，更具体地涉及有助于在集成电路中形成栅极期间减少线边缘粗糙度（LER）的系统和方法。公开了用于改善光致抗蚀剂线的临界尺寸（CD）的系统和方法，其包括有助于减轻LER的非光刻收缩组分，以及有助于实现和/或恢复目标临界尺寸的修剪蚀刻部件。

57. 发明授权

US07279386B2 Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions 失效
标题翻译：用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法
公开(公告)号：US07279386B2
公开(公告)日：2007-10-09
申请号：US11002586
申请日：2004-12-03
申请人： Mark C. Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
发明人： Mark C. Kelling , Douglas Bonser , Srikanteswara Dakshina-Murthy , Asuka Nomura
IPC分类号： H01L21/335
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/32139 , H01L29/66628 , H01L29/66659
摘要： A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
摘要翻译：在多晶硅栅电极上形成特定尺寸的间隔物的方法在选择性外延生长期间保护多晶硅栅电极的侧壁。无论是不对称的还是对称的，通过在限定多晶硅栅电极图案和图案中使用相同的特定曝光工具（例如193nm波长步长和扫描曝光工具）和相同的图案掩模版来精确限定间隔件，同时采用紧密对准规格。

58. 发明授权

US07148142B1 System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权
标题翻译：用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化
公开(公告)号：US07148142B1
公开(公告)日：2006-12-12
申请号：US10874500
申请日：2004-06-23
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A. Phan
IPC分类号： H01L21/44
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76817 , H01L2221/1021
摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.
摘要翻译：提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。电介质蚀刻将图案从转印层转移到电介质层中。然后，金属填充过程用金属填充介电层的双镶嵌开口。

59. 发明授权

US07105399B1 Selective epitaxial growth for tunable channel thickness 有权
标题翻译：选择性外延生长可调谐通道厚度
公开(公告)号：US07105399B1
公开(公告)日：2006-09-12
申请号：US11004951
申请日：2004-12-07
申请人： Srikanteswara Dakshina-Murthy , Douglas Bonser , Hans Van Meer , David Brown
发明人： Srikanteswara Dakshina-Murthy , Douglas Bonser , Hans Van Meer , David Brown
IPC分类号： H01L21/302 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84
摘要： Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.
摘要翻译：通过选择性外延生长形成具有选择性调谐的沟道厚度的栅极。实施例包括在SOI衬底中形成浅沟槽隔离区域，选择性地去除暴露的特定有源区域中的氮化物阻挡层和衬垫氧化物层，以及实现选择性外延生长以增加特定有源区域中的半导体层的厚度。随后，去除其它有源区中剩余的氮化物阻挡层和焊盘氧化物层，如通过热氧化形成栅介电层，并完成晶体管。

60. 发明授权

US06989332B1 Ion implantation to modulate amorphous carbon stress 失效
标题翻译：离子注入调节无定形碳应力
公开(公告)号：US06989332B1
公开(公告)日：2006-01-24
申请号：US10217730
申请日：2002-08-13
申请人： Scott A. Bell , Srikanteswara Dakshina-Murthy , Christopher F. Lyons
发明人： Scott A. Bell , Srikanteswara Dakshina-Murthy , Christopher F. Lyons
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , C23C16/26 , C23C16/56 , H01L21/0332
摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.
摘要翻译：一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。

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