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51. 发明申请

US20090279376A1 METHOD AND SYSTEM FOR SELECTIVELY LIMITING PEAK POWER CONSUMPTION DURING PROGRAMMING OR ERASE OF NON-VOLATILE MEMORY DEVICES 有权
标题翻译：在非易失性存储器件编程或擦除期间选择性限制峰值功耗的方法和系统
公开(公告)号：US20090279376A1
公开(公告)日：2009-11-12
申请号：US12505909
申请日：2009-07-20
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C16/0483
摘要： A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array.
摘要翻译：电源电路用于在存储器单元的编程或擦除期间向非易失性存储单元阵列提供具有有限峰值幅度的功率。电源电路包括提供具有预定大小的参考电流的参考电流源。参考电流源耦合到电流发生器，其向阵列提供电流。电流发生器可以使用电流镜，并且它向阵列提供与参考电流具有预定关系的电流。电流发生器由控制电路选择性地使能，使得在阵列中的至少一些存储器单元的编程或擦除期间将电流提供给阵列。

52. 发明授权

US07567462B2 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices 有权
标题翻译：用于在编程或擦除非易失性存储器件期间选择性地限制峰值功耗的方法和系统
公开(公告)号：US07567462B2
公开(公告)日：2009-07-28
申请号：US11601368
申请日：2006-11-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/0483
摘要： A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array.
摘要翻译：电源电路用于在存储器单元的编程或擦除期间向非易失性存储单元阵列提供具有有限峰值幅度的功率。电源电路包括提供具有预定大小的参考电流的参考电流源。参考电流源耦合到电流发生器，其向阵列提供电流。电流发生器可以使用电流镜，并且它向阵列提供与参考电流具有预定关系的电流。电流发生器由控制电路选择性地使能，使得在阵列中的至少一些存储器单元的编程或擦除期间将电流提供给阵列。

53. 发明授权

US07483305B2 Method, apparatus and system relating to automatic cell threshold voltage measurement 有权
标题翻译：与自动电池阈值电压测量相关的方法，设备和系统
公开(公告)号：US07483305B2
公开(公告)日：2009-01-27
申请号：US11511172
申请日：2006-08-28
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C29/52 , G11C16/04 , G11C16/26 , G11C29/12005 , G11C29/50004 , G11C2029/1204
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre-charge bit line reference circuit, and comparator and latch circuitry. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre-charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和装置。测量电路包括内部参考电流发生器，多个存储单元，预充电位线参考电路以及比较器和锁存电路。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。参考电流以大的步长产生，直到比较位线电压和预充电位线参考电压的比较器被切换为止。参考电流然后以小步骤产生电流，直到再次切换比较器。参考电流在10 nA的精度内收敛于存储单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明的实施例的存储器的系统。

54. 发明申请

US20080049495A1 Method, apparatus and system relating to automatic cell threshold voltage measurement 有权
标题翻译：与自动电池阈值电压测量相关的方法，设备和系统
公开(公告)号：US20080049495A1
公开(公告)日：2008-02-28
申请号：US11511172
申请日：2006-08-28
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C29/52 , G11C16/04 , G11C16/26 , G11C29/12005 , G11C29/50004 , G11C2029/1204
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre-charge bit line reference circuit, and comparator and latch circuitry. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre-charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和装置。测量电路包括内部参考电流发生器，多个存储单元，预充电位线参考电路以及比较器和锁存电路。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。参考电流以大的步长产生，直到比较位线电压和预充电位线参考电压的比较器被切换为止。参考电流然后以小步骤产生电流，直到再次切换比较器。参考电流在10 nA的精度内收敛于存储单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明的实施例的存储器的系统。

55. 发明授权

US07184338B2 Semiconductor device, semiconductor device testing method, and programming method 有权
标题翻译：半导体器件，半导体器件测试方法和编程方法
公开(公告)号：US07184338B2
公开(公告)日：2007-02-27
申请号：US11215253
申请日：2005-08-30
申请人： Harunobu Nakagawa , Minoru Aoki , Shigekazu Yamada
发明人： Harunobu Nakagawa , Minoru Aoki , Shigekazu Yamada
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.
摘要翻译：半导体器件包括：在测试模式下锁存给定信号的锁存电路; 以及产生电路，其根据锁存在锁存电路中的信号产生定义用于对存储器单元进行编程的编程电压的信号。所述发生电路包括：产生限定所述编程电压的初始电压的信号的电路; 产生定义编程电压的脉冲宽度的信号的电路; 以及当编程电压是逐步增加的电压时产生限定编程电压的步长的信号的电路。

56. 发明申请

US20060077736A1 Semiconductor device, semiconductor device testing method, and programming method 有权
标题翻译：半导体器件，半导体器件测试方法和编程方法
公开(公告)号：US20060077736A1
公开(公告)日：2006-04-13
申请号：US11215253
申请日：2005-08-30
申请人： Harunobu Nakagawa , Minoru Aoki , Shigekazu Yamada
发明人： Harunobu Nakagawa , Minoru Aoki , Shigekazu Yamada
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.
摘要翻译：半导体器件包括：在测试模式下锁存给定信号的锁存电路; 以及产生电路，其根据锁存在锁存电路中的信号产生定义用于对存储器单元进行编程的编程电压的信号。所述发生电路包括：产生限定所述编程电压的初始电压的信号的电路; 产生定义编程电压的脉冲宽度的信号的电路; 以及当编程电压是逐步增加的电压时产生限定编程电压的步长的信号的电路。

57. 发明申请

US20050213388A1 Semiconductor device and method for writing data into the semiconductor device 有权
标题翻译：用于将数据写入半导体器件的半导体器件和方法
公开(公告)号：US20050213388A1
公开(公告)日：2005-09-29
申请号：US11090716
申请日：2005-03-25
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454
摘要： A semiconductor device is provided which includes a memory part that includes memory cells having different threshold values; a read circuit that reads data from a memory cell to be programmed with write data that is input; and a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing. The pattern that causes erasing during the programming is processed as an inhibited operation. If the inhibited operation is identified, the process is forcedly terminated without initiating the programming by the write command. This makes it possible to avoid erasing resulting from the programming.
摘要翻译：提供一种半导体器件，其包括具有不同阈值的存储单元的存储器部分; 读取电路，用于从存储器单元读取要被输入的写入数据进行编程的数据; 以及检测电路，其将写入数据与从存储器单元读取的数据进行比较，从而检测数据的编程导致擦除的图案。在编程期间导致擦除的图案被处理为禁止操作。如果识别出禁止的操作，则强制终止该过程，而不通过写命令启动编程。这使得可以避免编程导致的擦除。

58. 发明授权

US06859393B1 Ground structure for page read and page write for flash memory 有权
标题翻译： Flash存储器的页面读取和页面写入的接地结构
公开(公告)号：US06859393B1
公开(公告)日：2005-02-22
申请号：US10264387
申请日：2002-10-04
申请人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
发明人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , G11C2216/14
摘要： A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.
摘要翻译：用于闪存的页面读取和页面写入的接地结构。闪存单元的阵列结构包括多个扇区。每个扇区包括I / O块加参考阵列和冗余单元阵列。每个I / O块包括子I / O块。 I / O块内的每个子I / O块以及包括参考单元，冗余单元和边缘结构的其他结构都耦合到独特的接地参考信号。这些独特的接地参考信号可以选择性地耦合到系统接地或偏置的接地参考。这种新颖的接地布置使得能够同时读取来自每个子I / O块的一个位的页面读取操作。另外，每个I / O块的一位可以同时编程。此外，可以选择性地调整阵列的单元的接地参考电压以优化操作。

59. 发明授权

US06816423B2 System for control of pre-charge levels in a memory device 有权
标题翻译：用于控制存储器件中的预充电水平的系统
公开(公告)号：US06816423B2
公开(公告)日：2004-11-09
申请号：US10136034
申请日：2002-04-29
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C700
CPC分类号： G11C16/0475 , G11C7/12 , G11C16/24
摘要： System to control a pre-charge level of a dual bit cell in a memory device. The system includes apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.
摘要翻译：用于控制存储器件中的双位单元的预充电水平的系统。该系统包括耦合在第一和第二存储器单元之间的第一端子和耦合到第二存储器单元的第二端子的装置。该装置还包括耦合到第一和第二端子的镜电路，其中镜电路操作以在第一和第二端子上保持相同的电压电平。

60. 发明授权

US08760933B2 Circuits, systems, and methods for driving high and low voltages on bit lines in non-volatile memory 有权
标题翻译：用于在非易失性存储器中的位线上驱动高低电压的电路，系统和方法
公开(公告)号：US08760933B2
公开(公告)日：2014-06-24
申请号：US13610512
申请日：2012-09-11
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C16/06 , G11C7/12 , G11C16/24
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30
摘要： An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.
摘要翻译：集成电路位线驱动器系统包括耦合到非易失性存储器单元阵列的相应位线的多个位线驱动器。每个位线驱动器包括偏置晶体管，输入信号通过偏置晶体管耦合到相应的位线。位线驱动器系统包括偏置电压电路，其产生耦合到偏置晶体管的各个栅极的偏置电压。偏置电压电路最初加速晶体管栅极的充电，随后以较慢的速率完成对栅极的充电。使用具有与偏置晶体管的电特性匹配的电特性的二极管耦合晶体管产生偏置电压，使得偏置电压以与偏置晶体管的阈值电压变化相同的方式随集成电路的过程或温度变化而变化过程或温度变化。

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