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51. 发明授权

US5019771A Contact sensing for integrated circuit testing 失效
标题翻译：接触式感测用于集成电路测试
公开(公告)号：US5019771A
公开(公告)日：1991-05-28
申请号：US527661
申请日：1990-05-21
申请人： Tsen-Shau Yang , Ger-Chih Chou , Fu-Chieh Hsu
发明人： Tsen-Shau Yang , Ger-Chih Chou , Fu-Chieh Hsu
IPC分类号： G01R1/067
CPC分类号： G01R1/06794
摘要： A technique for detecting whether electrical contact between a probe tip and a device under test ("DUT") has been established. A contact sensing circuit has a ground that is isolated from the ground of the DUT (and remaining portions of the test equipment) during contact sensing. The contact sensing circuit has elements that operate to apply a characteristic signal to one of the DUT terminals, such as its ground terminal. This causes virtually all the DUT circuit traces to track the applied signal (relative to the contact sensing ground). The contact sensing circuit further includes elements, coupled to the probe, that operate to detect the presence of the characteristic signal (relative to the contact sensing ground) on the probe. Once electrical contact has been established, the characteristic signal output is disconnected from the DUT, the test equipment ground is connected to the contact sensing circuit ground, and the probe output is coupled to the relevant portions of the test equipment circuitry.
摘要翻译：用于检测探针尖端和被测设备（“DUT”）之间的电接触是否已建立的技术。接触检测电路在接触检测期间具有与DUT的接地（和测试设备的剩余部分）隔离的接地。接触检测电路具有操作以将特征信号施加到诸如其接地端子的DUT端子之一的元件。这导致几乎所有DUT电路迹线跟踪所施加的信号（相对于接触感测地）。接触感测电路还包括耦合到探头的元件，其操作以检测探针上的特征信号（相对于接触感应接地）的存在。一旦建立了电气接触，特征信号输出与DUT断开连接，测试设备的地线连接到接触感应电路地，探头输出端连接到测试设备电路的相关部分。

52. 发明授权

US4843023A Process for forming lightly-doped-drain (LDD) without extra masking steps 失效
标题翻译：用于形成轻掺杂漏极（LDD）的工艺，无需额外的掩模步骤
公开(公告)号：US4843023A
公开(公告)日：1989-06-27
申请号：US65617
申请日：1987-06-30
申请人： Kuang Y. Chiu , Fu-Chieh Hsu
发明人： Kuang Y. Chiu , Fu-Chieh Hsu
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/0337 , H01L21/823864 , H01L29/6656 , H01L29/78
摘要： A new lightly doped drain (LDD) process which does not required extra masking steps as compared to the conventional CMOS process is presented. By employing a new two layer side wall spacer technology, the LDD ion implantation for n-channel and p-channel devices can be carried out by sharing the n.sup.+ or p.sup.+ source and drain ion implantation mask. This approach provides maximum flexibility in designing optimum n.sup.- and p.sup.- channel LDD MOSFETs without using any additional mask steps other than the conventional CMOS mask levels. This process is also compatible with self-aligned silicide process.
摘要翻译：提出了与常规CMOS工艺相比不需要额外掩模步骤的新的轻掺杂漏极（LDD）工艺。通过采用新的双层侧壁间隔技术，n沟道和p沟道器件的LDD离子注入可以通过共享n +或p +源极和漏极离子注入掩模进行。这种方法在设计最佳的n沟道和p沟道LDD MOSFET时提供了最大的灵活性，而不需要采用常规CMOS掩模级别以外的任何附加掩模步骤。该工艺也与自对准硅化物工艺兼容。

53. 发明申请

US20100329061A1 ELECTRICAL FUSE CIRCUIT FOR SECURITY APPLICATIONS 有权
标题翻译：用于安全应用的电气保险丝电路
公开(公告)号：US20100329061A1
公开(公告)日：2010-12-30
申请号：US12881944
申请日：2010-09-14
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

54. 发明授权

US07634707B2 Error detection/correction method 失效
标题翻译：误差检测/校正方法
公开(公告)号：US07634707B2
公开(公告)日：2009-12-15
申请号：US10800382
申请日：2004-03-11
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.
摘要翻译：一种用于错误检测和校正（EDC）的方法包括：响应于数据包产生完整的EDC码; 在数据分组中分发完整的EDC代码以创建多个字节，每个字节包括来自数据分组的数据部分和来自完整EDC代码的EDC代码部分; 将字节存储在存储器模块中; 从存储器模块检索字节; 将从存储器模块检索的字节的数据部分转发到请求设备; 将从存储器模块检索的字节的数据部分提供给EDC功能块; 将从存储器模块检索的字节的EDC代码部分提供给EDC功能块; 并且在从所提供的EDC代码部分接收到完整的EDC代码时，在EDC功能块中执行错误校验和校正。

55. 发明申请

US20050074935A1 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same 失效
标题翻译：用常规逻辑过程的轻微修改制造的非易失性存储器单元及其操作方法
公开(公告)号：US20050074935A1
公开(公告)日：2005-04-07
申请号：US10999259
申请日：2004-11-29
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： G11C7/20 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/8238
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.
摘要翻译：使用常规逻辑过程制造非易失性存储器单元，并进行微小修改。通过在半导体衬底的阱区域中形成浅沟槽隔离（STI）区域来制造电池。在STI区域中形成凹陷区域，其中凹入区域延伸到STI区域中并且暴露出阱区域中的侧壁区域。在侧壁区域中形成电容器区域。在阱区域上形成介电层，包括侧壁区域。然后在电介质层上形成栅电极，其中栅电极的一部分延伸到凹陷区域中。然后以相对于栅电极的自对准方式形成电池的存取晶体管。电容器结构由栅电极（凹陷区域），侧壁区域的电介质层和电容器区域形成。

56. 发明申请

US20050044467A1 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US20050044467A1
公开(公告)日：2005-02-24
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G06F11/10 , G11C29/00 , H03M13/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

57. 发明授权

US06841821B2 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same 失效
公开(公告)号：US06841821B2
公开(公告)日：2005-01-11
申请号：US10355477
申请日：2003-01-31
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： G11C7/20 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/108
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.

58. 发明授权

US06642098B2 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US06642098B2
公开(公告)日：2003-11-04
申请号：US10374917
申请日：2003-02-25
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L218242
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

59. 发明授权

US06512691B2 Non-volatile memory embedded in a conventional logic process 失效
公开(公告)号：US06512691B2
公开(公告)日：2003-01-28
申请号：US10165589
申请日：2002-06-07
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell fabricated using a conventional logic process. As used herein, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses only one layer of polysilicon. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) commonly available in a conventional logic process. This non-volatile memory cell can be programmed and erased using relatively low voltages. As a result, the voltages required to program and erase can be provided by transistors readily available in a conventional logic process. The program and erase voltages are precisely controlled to avoid the need for a triple-well process. In one embodiment, the non-volatile memory cells are configured to form a non-volatile memory block that is used in a system-on-a-chip. In this embodiment, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the thin oxide non-volatile memory cells are improved.

60. 发明授权

US06468855B2 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same 有权
标题翻译：使用修改的逻辑过程制造的减少的地形DRAM单元和用于操作的方法
公开(公告)号：US06468855B2
公开(公告)日：2002-10-22
申请号：US09772434
申请日：2001-01-29
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L218242
CPC分类号： G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shall P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.
摘要翻译：一种包括具有存取晶体管和存储电容器的DRAM单元的存储器系统。存储电容器通过形成多晶硅冠电极，覆盖多晶硅冠的电介质层和覆盖在电介质层上的多晶硅板电极来制造。在形成存储电容器期间执行第一组热循环以形成和退火电容器结构的元件。随后，通过离子注入形成P +和/或N +区，形成金属硅化物。结果，形成电容器结构所需的相对较高的第一组热循环不会对浅的P +和N +区域或金属硅化物产生不利影响。在浅区域和金属硅化物的形成期间执行第二组热循环，其与第一组热循环相当或者小于第一组热循环。

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