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51. 发明授权

US08392779B2 Interface voltage adjustment based on error detection 有权
标题翻译：基于错误检测的接口电压调整
公开(公告)号：US08392779B2
公开(公告)日：2013-03-05
申请号：US12109826
申请日：2008-04-25
申请人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
发明人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00
CPC分类号： G11C29/021 , G06F11/1004 , G11C7/1006 , G11C11/401 , G11C11/4074 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2029/0411 , H03M13/03
摘要： A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.
摘要翻译：调整接口电压的方法包括在存储器件和控制器之间传输数据，以及检测数据传输中是否发生错误。基于检测来调整存储器件和控制器中的至少一个的接口电压。

52. 发明申请

US20090271678A1 INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION 有权
标题翻译：基于错误检测的接口电压调整
公开(公告)号：US20090271678A1
公开(公告)日：2009-10-29
申请号：US12109826
申请日：2008-04-25
申请人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
发明人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
IPC分类号： H03M13/00 , G06F11/07
CPC分类号： G11C29/021 , G06F11/1004 , G11C7/1006 , G11C11/401 , G11C11/4074 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2029/0411 , H03M13/03
摘要： A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.
摘要翻译：调整接口电压的方法包括在存储器件和控制器之间传输数据，以及检测数据传输中是否发生错误。基于检测来调整存储器件和控制器中的至少一个的接口电压。

53. 发明授权

US08125812B2 Method and device for transmitting outgoing useful signals and an outgoing clock signal 有权
标题翻译：用于发送输出有用信号和输出时钟信号的方法和装置
公开(公告)号：US08125812B2
公开(公告)日：2012-02-28
申请号：US12058899
申请日：2008-03-31
申请人： Martin Streibl , Peter Gregorius , Ralf Schledz
发明人： Martin Streibl , Peter Gregorius , Ralf Schledz
IPC分类号： G11C5/02
CPC分类号： G11C7/22 , G06F1/10 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.
摘要翻译：用于发送输出有用信号和输出时钟信号的方法和装置。有用的信号和时钟信号从发射机经由第一线对和第二线对发射到接收机。第一有用信号以第一线对的电位之间的调制差的形式发送。第二有用信号以第二线对的电位之间的调制差的形式传输。时钟信号以第一线对的电位的平均值与第二线对的电位的平均值之间的调制差的形式发送。

54. 发明授权

US08031539B2 Memory device and memory system comprising a memory device and a memory control device 有权
标题翻译：存储器件和存储器系统，包括存储器件和存储器控制器件
公开(公告)号：US08031539B2
公开(公告)日：2011-10-04
申请号：US12248759
申请日：2008-10-09
申请人： Peter Gregorius
发明人： Peter Gregorius
IPC分类号： G11C7/00
CPC分类号： G11C5/00 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.
摘要翻译：在一个实施例中，存储器件包括时钟产生单元，其被配置为产生读取时钟信号，所述时钟产生单元连接到被配置为发送读取时钟信号的第一时钟信号触点，并且所述时钟产生单元连接到数据信号触点被配置为发送数据信号，所述存储器件被配置为相对于读时钟信号以相位和频率精确（源同步）方式发送数据信号。

55. 发明授权

US07908232B2 Training connections in a memory arrangement 有权
标题翻译：训练连接在内存安排
公开(公告)号：US07908232B2
公开(公告)日：2011-03-15
申请号：US11844791
申请日：2007-08-24
申请人： Peter Gregorius
发明人： Peter Gregorius
IPC分类号： G06F15/18
CPC分类号： G06F13/1684
摘要： A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.
摘要翻译：训练存储器装置中的连接的方法包括训练存储器部分和控制器的接收器部分之间的连接，用于在存储器装置的元件之间的基本上所有其他连接的训练之前或同时进行控制，训练有素

56. 发明授权

US07587655B2 Method of transferring signals between a memory device and a memory controller 有权
标题翻译：在存储器件和存储器控制器之间传送信号的方法
公开(公告)号：US07587655B2
公开(公告)日：2009-09-08
申请号：US11259376
申请日：2005-10-26
申请人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
发明人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
IPC分类号： G11C29/00
CPC分类号： G11C8/18
摘要： Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.
摘要翻译：用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。

57. 发明授权

US07474876B2 Device for the production of standard-compliant signals 有权
标题翻译：用于生产标准兼容信号的设备
公开(公告)号：US07474876B2
公开(公告)日：2009-01-06
申请号：US10916776
申请日：2004-08-12
申请人： Jörg Bonhaus , Thomas Duda , Lajos Gazsi , Peter Gregorius
发明人： Jörg Bonhaus , Thomas Duda , Lajos Gazsi , Peter Gregorius
IPC分类号： H04B17/00 , H03C1/62
CPC分类号： H04L27/368
摘要： A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24). Moreover, the invention provides attenuating means (50) for attenuation of the signal dependent on the characteristics of the telecommunication channel.
摘要翻译：用于生产标准兼容信号（例如电信网络中的脉冲型信号）的装置用于以特定信号形式产生和适应和/或预失真信号，该特定信号形式取决于指定的标准信号形式在一个标准。该装置包括用于产生具有特定信号形式的信号的信号产生装置（10）和用于信号的自适应或预失真的信号调节装置（20）。根据本发明的信号产生装置（10）通过使用可编程移位寄存器（14）进行数字实现，该可编程移位寄存器（14）包含用于与数字输入信号（1）相乘的标准信号形式指定的乘法器。信号调节装置（20）包括数字滤波器（22）与下游多路复用器（24）的串行连接形式的基本上可伸缩的数字滤波器装置。此外，本发明提供衰减装置（50），用于根据电信信道的特性衰减信号。

58. 发明授权

US07450649B2 Current mode digital data transmitter 有权
标题翻译：电流模式数字数据发送器
公开(公告)号：US07450649B2
公开(公告)日：2008-11-11
申请号：US10481856
申请日：2003-05-15
申请人： Peter Gregorius , Armin Hanneberg
发明人： Peter Gregorius , Armin Hanneberg
IPC分类号： H04B3/00
CPC分类号： H04L25/0266 , H04L25/085
摘要： The invention relates to a transmitter for transmission of digital data via a transmission line (10), comprising a current-driving digital/analogue converter (1) which is arranged at the input of the transmitter; a current-operated form filter (2) for forming the current pulses which are supplied from the digital/analogue converter; a line driver (5) which carries out current/voltage conversion; and a circuit for offset compensation (6), which is arranged in a feedback path (11). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.
摘要翻译：本发明涉及一种用于经由传输线（10）传输数字数据的发射机，包括布置在发射机输入端的电流驱动数/模转换器（1）用于形成从数字/模拟转换器提供的电流脉冲的电流操作形式滤波器（2）执行电流/电压转换的线路驱动器（5）; 以及布置在反馈路径（11）中的偏移补偿电路（6）。为了提高在发射机的输出端发送的脉冲的质量，本发明提出了在目前的基础上进行发射机的内部信号处理。

59. 发明申请

US20080222443A1 Controller 审中-公开
标题翻译：控制器
公开(公告)号：US20080222443A1
公开(公告)日：2008-09-11
申请号：US11813952
申请日：2006-01-04
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： G06F1/08
CPC分类号： H03M9/00
摘要： The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).
摘要翻译：本发明涉及一种与时钟信号（clk_hr_i）同步控制的与设备（1）输入的连续时钟信号（clk_hr_i）同步的控制信号（evload_o，odload_o，st_chgclk_o，clk_o，st_chgclk_o，clk_o，stkorfiford_i），其中所述控制器（SE）具有：寄存器装置，用于登记包括多个位位置的至少一个设置信号（st_load_i，st_fiford_i），用于根据一个或多个位位置对时钟信号（clk_hr_i）的边沿进行计数的计数装置设置分别登记在寄存器装置中的信号，以及同步和输出装置，用于使由计数装置计数的值与时钟信号（clk_hr_i）和登记的设置信号同步，并输出至少一个控制信号，其中寄存器装置，计数装置和同步和输出装置被配置和彼此连接，使得输出控制信号取决于相应的有效登记的设定信号占据（占据）多个时间位置中的一个，具有与时钟信号的前沿或后沿同步的半个时钟周期的整数倍的相位差。控制器可以特别用于控制同步并行 - 串行转换器，用于将包括k位位置的并行输入信号转换为与时钟信号（clk_hr_i）同步的串行输出信号序列，该时钟信号（clk_hr_i）被提供在发送电路中接口电路的即将到来的存储器生成（例如DDR4）的非常快的DDR DRAM半导体存储器组件。

60. 发明授权

US07269093B2 Generating a sampling clock signal in a communication block of a memory device 有权
标题翻译：在存储器件的通信块中生成采样时钟信号
公开(公告)号：US07269093B2
公开(公告)日：2007-09-11
申请号：US11264060
申请日：2005-10-31
申请人： Peter Gregorius , Martin Streibl
发明人： Peter Gregorius , Martin Streibl
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G11C7/222
摘要： A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a local clock signal having a predetermined phase relationship with respect to the input clock signal, and generating the sampling clock signal based on the local clock signal.
摘要翻译：一种方法在具有分布在存储器件中的多个通信块的存储器件的通信块中产生采样时钟信号。该方法包括在通信块中接收输入时钟信号，仅响应于输入时钟信号产生相对于输入时钟信号具有预定相位关系的本地时钟信号，并且基于该时钟信号产生采样时钟信号本地时钟信号。

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