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51. 发明申请

US20090224335A1 FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT 失效
标题翻译：具有减少的低温分离分离诱发的漏电流的场效应晶体管
公开(公告)号：US20090224335A1
公开(公告)日：2009-09-10
申请号：US12041967
申请日：2008-03-04
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译：沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。

52. 发明申请

US20080303105A1 DUAL GATE DIELECTRIC SRAM 失效
标题翻译：双门电介质SRAM
公开(公告)号：US20080303105A1
公开(公告)日：2008-12-11
申请号：US11759538
申请日：2007-06-07
申请人： Leland Chang , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/44
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance.
摘要翻译：提供了包含具有比NFET栅极电介质更厚的有效氧化物厚度（EOT）的PFET栅极电介质的SRAM单元结构及其制造方法。 PFET栅极电介质和NFET栅极电介质可以是氮氧化硅层，CVD氧化物层或具有不同厚度的高K电介质层。 PFET栅极电介质可以是两个电介质层的堆叠，并且NFET栅极电介质可以是两个电介质层中的一个。 PFET栅极电介质的更大的EOT产生上拉PFET的导通电流的降低，以获得最佳的SRAM性能。

53. 发明申请

US20080248615A1 CMOS STRUCTURE FOR BODY TIES IN ULTRA-THIN SOI (UTSOI) SUBSTRATES 失效
标题翻译：超薄SOI（UTSOI）衬底中的体型的CMOS结构
公开(公告)号：US20080248615A1
公开(公告)日：2008-10-09
申请号：US11925136
申请日：2007-10-26
申请人： Jeffrey W. Sleight
发明人： Jeffrey W. Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L21/76229 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects.
摘要翻译：本发明提供一种半导体结构，其包括具有UTSOI区域和体积-Si区域的衬底，其中UTSOI区域和体积-Si区域具有相同的晶体取向; 将UTSOI区域与体Si区域分离的隔离区域; 以及位于UTSOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 UTSOI区域在绝缘层顶上具有SOI层，其中SOI层的厚度小于约40nm。体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。

54. 发明申请

US20080164535A1 CURVED FINFETS 有权
标题翻译：弯曲的熔体
公开(公告)号：US20080164535A1
公开(公告)日：2008-07-10
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

55. 发明授权

US07396776B2 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US07396776B2
公开(公告)日：2008-07-08
申请号：US11483901
申请日：2006-07-10
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

56. 发明授权

US09343142B2 Nanowire floating gate transistor 有权
标题翻译：纳米线浮栅晶体管
公开(公告)号：US09343142B2
公开(公告)日：2016-05-17
申请号：US13344517
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L29/788 , G11C11/56 , H01L21/28 , H01L29/423 , H01L29/06
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/0673 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
摘要翻译：浮栅晶体管，存储单元及其制造方法。浮栅晶体管包括一个或多个基本上圆柱形的选通线。浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。

57. 发明授权

US08822278B2 Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US08822278B2
公开(公告)日：2014-09-02
申请号：US13434128
申请日：2012-03-29
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，一种用于制造FET器件的方法包括以下步骤。提供晶片。使用STI在晶片中形成多个有效区域。在晶片上形成多个栅极堆叠，其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少给定的一个有源区域，给定的源极侧的栅极到栅极间隔有源面积大于给定有源区域的漏极侧上的栅极至栅极间距。隔板形成在栅极堆叠的相对侧上。在给定活动区域的源侧执行成角度的植入物。还提供了FET器件。

58. 发明授权

US08723162B2 Nanowire tunnel field effect transistors 有权
标题翻译：纳米线隧道场效应晶体管
公开(公告)号：US08723162B2
公开(公告)日：2014-05-13
申请号：US13541022
申请日：2012-07-03
申请人： Sarunya Bangsaruntip , Isaac Lauer , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Isaac Lauer , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.
摘要翻译：纳米线隧道场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有第一远端和第二远端的硅部分，硅部分被围绕硅部分周向设置的栅极结构围绕，漏极区域包括从第一远端延伸的掺杂硅部分，布置在沟道区域中的掺杂硅部分的一部分，由硅部分的第二远端限定的空腔和栅极结构的内径，以及源区域，从空腔中的硅部分的第二远端外延延伸的掺杂外延硅部分，第一焊盘区域和硅衬底的一部分。

59. 发明授权

US08722472B2 Hybrid CMOS nanowire mesh device and FINFET device 有权
标题翻译：混合CMOS纳米线网格器件和FINFET器件
公开(公告)号：US08722472B2
公开(公告)日：2014-05-13
申请号：US13328015
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the FINFET device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和FINFET器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和FINFET器件的半导体结构。

60. 发明授权

US08716072B2 Hybrid CMOS technology with nanowire devices and double gated planar devices 失效
标题翻译：具有纳米线器件和双门控平面器件的混合CMOS技术
公开(公告)号：US08716072B2
公开(公告)日：2014-05-06
申请号：US13189999
申请日：2011-07-25
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L29/775
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/045 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/513 , H01L29/66439 , H01L29/66772 , H01L29/78648 , H01L29/78696
摘要： A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.
摘要翻译：衬底包括第一源极区域和第一漏极区域，每个第一漏极区域具有设置在第二半导体层上的第一半导体层和平行于{110}晶面的平面和平行于{110}晶面的相对侧壁表面的表面; 纳米线通道部件由第一源极区域和第一漏极区域悬挂，其中纳米线通道构件包括第一半导体层，以及平行于{100}晶面的相对侧壁表面和平行于{110}晶面的相对面。衬底还包括具有第一源极和漏极区域的特性的第二源极和漏极区域以及由第二源极区域和第二漏极区域悬置并且具有与纳米线通道构件相同的特性的单个沟道构件。单通道构件的宽度是单个纳米线构件的宽度的至少几倍。

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