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51. 发明申请

US20060055043A1 Connection structure for semiconductor devices 有权
标题翻译：半导体器件的连接结构
公开(公告)号：US20060055043A1
公开(公告)日：2006-03-16
申请号：US10939931
申请日：2004-09-13
申请人： Jhon Liaw , Sung-Chun Hsieh , Wesley Lin , Chii-Ming Wu , Ren-Fen Tsui
发明人： Jhon Liaw , Sung-Chun Hsieh , Wesley Lin , Chii-Ming Wu , Ren-Fen Tsui
IPC分类号： H01L29/40
CPC分类号： H01L21/76843 , H01L21/76816 , H01L21/76844 , H01L21/76846 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two of the one or more wide areas; and a conductive plug for filling at least partially the peanut-shaped opening.
摘要翻译：本公开一般涉及半导体器件的制造，更具体地，涉及用于半导体器件的改进的连接结构。半导体器件的连接结构包括：花生形开口，其包括狭窄区域和一个或多个宽阔区域，其中所述狭窄区域在所述一个或多个宽区域中的两个之间; 以及用于至少部分地填充花生形开口的导电插塞。

52. 发明申请

US20050038684A1 System and method of demand and capacity management 有权
标题翻译：需求和能力管理的制度和方法
公开(公告)号：US20050038684A1
公开(公告)日：2005-02-17
申请号：US10640776
申请日：2003-08-14
申请人： Chung-Wen Wang , Chii-Ming Wu , Edwin Liou , Chiang-Sheng Chin
发明人： Chung-Wen Wang , Chii-Ming Wu , Edwin Liou , Chiang-Sheng Chin
IPC分类号： G06F17/60
CPC分类号： G06Q10/06 , G06Q10/06315 , G06Q10/087 , Y02P90/20
摘要： A new business model of supply chain management for IC foundry and a system and method of demand and capacity management with machine-time accuracy are provided. The system includes an allocation planning module, an order management module, a capacity model, and a capacity management module. The allocation planning module receives a demand plan for a product. The capacity management module transforms the demand plan into a machine-time-based plan according to the capacity model, and reserves capacity according to the machine-time-based plan for the demand plan. The capacity management module further transforms a purchase order received by the order management module before a cutoff date for the product into a machine-time-based order, accepts the machine-time-based order and decreases the reservation capacity depending on the machine-time-based plan.
摘要翻译：提供了IC铸造供应链管理的新业务模式，并提供了机器时间精度的需求和容量管理系统和方法。该系统包括分配规划模块，订单管理模块，容量模型和容量管理模块。分配计划模块接收产品的需求计划。容量管理模块根据容量模型将需求计划转换为基于机器的计划，并根据基于机器时间的需求计划计划预留容量。容量管理模块进一步将订单管理模块接收到的采购订单转换为产品的截止日期为基于机器时间的订单，接受基于机器时间的订单，并根据机器时间降低预留容量的计划

53. 发明授权

US08592915B2 Doped oxide for shallow trench isolation (STI) 有权
标题翻译：用于浅沟槽隔离（STI）的掺杂氧化物
公开(公告)号：US08592915B2
公开(公告)日：2013-11-26
申请号：US13012948
申请日：2011-01-25
申请人： Yu-Lien Huang , Chun Hsiung Tsai , Chii-Ming Wu , Ziwei Fang
发明人： Yu-Lien Huang , Chun Hsiung Tsai , Chii-Ming Wu , Ziwei Fang
IPC分类号： H01L29/76
CPC分类号： H01L21/76237 , H01L21/02321 , H01L21/31111 , H01L21/31155 , H01L21/76224
摘要： The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.
摘要翻译：所描述的实施例提供了用碳掺杂氧化物的方法和结构，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。硬掩模层可用于保护下面的硅不被掺杂。通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

54. 发明申请

US20130049219A1 Semiconductor Device and Method for Forming the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130049219A1
公开(公告)日：2013-02-28
申请号：US13222502
申请日：2011-08-31
申请人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-ta Lei
发明人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-ta Lei
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L29/78 , H01L21/02063 , H01L21/28512 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L23/485 , H01L23/535 , H01L29/41775 , H01L29/45 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.
摘要翻译：提供了一种用于形成和使用衬套的系统和方法。一个实施例包括在衬底之上的层间电介质中形成开口，并沿着开口的侧壁形成衬垫。衬套的一部分从开口的底部移除，并且可以通过衬套执行清洁过程。通过使用衬垫，可以减少或消除从清洁过程对开口侧壁的损坏。另外，衬垫可用于帮助衬底内的离子注入。

55. 发明申请

US20120112248A1 MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION 有权
标题翻译：形成超声结构的机制
公开(公告)号：US20120112248A1
公开(公告)日：2012-05-10
申请号：US12941509
申请日：2010-11-08
申请人： Chii-Ming Wu , Yu Lien Huang , Chun Hsiung Tsai
发明人： Chii-Ming Wu , Yu Lien Huang , Chun Hsiung Tsai
IPC分类号： H01L29/78 , H01L21/265
CPC分类号： H01L29/7831 , H01L21/2236 , H01L21/823418 , H01L21/823431 , H01L29/66795 , H01L29/66803
摘要： The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.
摘要翻译：方法和结构的实施例用于通过等离子体掺杂工艺掺杂鳍结构，以形成浅掺杂的源极和漏极（LDD）区域。该方法涉及两步等离子体掺杂工艺。第一级等离子体工艺使用重载气，例如原子量等于或大于约20amu的载气，以使翅片结构的表面无定形并且降低掺杂速率对晶体取向的依赖性。第二级等离子体处理使用比用于第一级等离子体处理的载气轻的载气，以将掺杂剂更深地驱动到鳍结构中。两级等离子体掺杂工艺在翅片结构的外表面下方产生均匀的掺杂剂分布。

56. 发明申请

US20070194409A1 Method of manufacturing semiconductor device with crack prevention ring 有权
标题翻译：具有防裂环的半导体器件制造方法
公开(公告)号：US20070194409A1
公开(公告)日：2007-08-23
申请号：US11788208
申请日：2007-04-19
申请人： Ping-Wei Wang , Chii-Ming Wu
发明人： Ping-Wei Wang , Chii-Ming Wu
IPC分类号： H01L23/544
CPC分类号： H01L23/562 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process.
摘要翻译：在集成电路的外部边缘处的防裂环防止在将集成电路分离成单个管芯期间的分层和破裂。防裂环垂直延伸到半导体工件中至少到集成电路的金属化层。防裂环可以与集成电路的测试焊盘的形成同时形成。防裂环可以部分或完全填充导电材料。可以在集成电路的钝化层下方的防裂环内形成气穴。在切割过程中可以除去防裂环。

57. 发明申请

US20060012012A1 Semiconductor device with crack prevention ring and method of manufacture thereof 有权
标题翻译：具有防裂环的半导体器件及其制造方法
公开(公告)号：US20060012012A1
公开(公告)日：2006-01-19
申请号：US10891955
申请日：2004-07-15
申请人： Ping-Wei Wang , Chii-Ming Wu
发明人： Ping-Wei Wang , Chii-Ming Wu
IPC分类号： H01L23/544
CPC分类号： H01L23/562 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a crack prevention ring at the exterior edge of an integrated circuit to prevent delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process. An optional seal ring may be formed between the crack prevention ring and the integrated circuit.
摘要翻译：在集成电路的外部边缘处形成防裂环的方法，以防止在将集成电路分离成单个管芯期间的分层和破裂。防裂环垂直延伸到半导体工件中至少到集成电路的金属化层。防裂环可以与集成电路的测试焊盘的形成同时形成。防裂环可以部分或完全填充导电材料。可以在集成电路的钝化层下方的防裂环内形成气穴。在切割过程中可以除去防裂环。可以在防裂环和集成电路之间形成可选的密封环。

58. 发明授权

US08383513B2 Asymmetric rapid thermal annealing to reduce pattern effect 有权
标题翻译：不对称快速热退火降低图案效果
公开(公告)号：US08383513B2
公开(公告)日：2013-02-26
申请号：US12898037
申请日：2010-10-05
申请人： Chun Hsiung Tsai , Chii-Ming Wu , Da-Wen Lin
发明人： Chun Hsiung Tsai , Chii-Ming Wu , Da-Wen Lin
IPC分类号： H01L21/44 , H01L21/8238
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/67248
摘要： Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.
摘要翻译：提供了用于退火图案化衬底的快速热退火方法和系统，对衬底温度的不均匀性具有最小的图案效应。快速热退火系统包括前侧加热源和背面加热源。快速热退火系统的背面加热源提供显着的热量以使衬底温度达到峰值退火温度。前侧加热源有助于将基板前侧附近的环境加热至比峰退火温度低约100℃至约200℃的温度。用于快速热退火的不对称前侧和后侧加热减少或消除图案效应，并提高WIW和WID器件的性能均匀性。

59. 发明申请

US20110212590A1 HIGH TEMPERATURE IMPLANTATION METHOD FOR STRESSOR FORMATION 审中-公开
标题翻译：用于压力容器形成的高温植入方法
公开(公告)号：US20110212590A1
公开(公告)日：2011-09-01
申请号：US12713735
申请日：2010-02-26
申请人： Chii-Ming Wu , Chun-Feng Nieh
发明人： Chii-Ming Wu , Chun-Feng Nieh
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/2658 , H01L29/66545 , H01L29/6659 , H01L29/7848
摘要： An integrated circuit device and method of fabricating the integrated circuit device is disclosed. According to one of the broader forms of the invention, a method involves providing a semiconductor substrate. A combination of a pre-amorphous implantation process, a high temperature carbon implantation process, and/or an annealing process are performed on the substrate to form a stressor region.
摘要翻译：公开了一种集成电路器件及其制造方法。根据本发明的更广泛形式之一，涉及提供半导体衬底的方法。在基板上进行预非晶注入工艺，高温碳注入工艺和/或退火工艺的组合以形成应力区域。

60. 发明授权

US07795119B2 Flash anneal for a PAI, NiSi process 有权
标题翻译：用于PAI，NiSi工艺的闪光退火
公开(公告)号：US07795119B2
公开(公告)日：2010-09-14
申请号：US11779187
申请日：2007-07-17
申请人： Chia Ping Lo , Jerry Lai , Chii-Ming Wu , Mei-Yun Wang , Da-Wen Lin
发明人： Chia Ping Lo , Jerry Lai , Chii-Ming Wu , Mei-Yun Wang , Da-Wen Lin
IPC分类号： H01L21/04
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/28052 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate.
摘要翻译：介绍了一种用于缓解MOSFET源极/漏极区域所引起的损害的结构和方法。提供具有栅极结构的衬底，该栅极结构包括栅极氧化物层和栅极电极层，以及已经注入有杂质离子的源极和漏极区域。 PAI工艺在源极和漏极区域内产生非晶层。沉积金属并反应以在非晶层内产生硅化物，而不会加剧现有的缺陷。然后通过对基板进行快速退火来回收源区和漏区的电导率。

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