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51. 发明授权

US06975006B2 Semiconductor device with modified channel compressive stress 失效
标题翻译：具有改变通道压应力的半导体器件
公开(公告)号：US06975006B2
公开(公告)日：2005-12-13
申请号：US10627849
申请日：2003-07-25
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/49 , H01L31/119
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device includes a substrate and a gate region on top of a substrate. First and second gate sidewall liners are situated on first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. First and second recessed spacers are situated on top of the first and second sidewall liners respectively. The height of the first and second spacers is lower than the height of the gate sidewall liner whereas the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.
摘要翻译：半导体器件包括衬底和位于衬底顶部上的栅极区域。第一和第二栅极侧壁衬里分别位于栅极区域的第一和第二侧上，第一和第二侧壁衬里具有接触栅极区域的侧壁和接触衬底的水平部分的垂直部分。第一和第二凹陷垫片分别位于第一和第二侧壁衬里的顶部上。第一和第二间隔件的高度低于栅极侧壁衬套的高度，而侧壁衬套的水平部分的宽度比间隔件的宽度短。

52. 发明授权

US06255023B1 Method of manufacturing binary phase shift mask 有权
标题翻译：制造二元相移掩模的方法
公开(公告)号：US06255023B1
公开(公告)日：2001-07-03
申请号：US09434046
申请日：1999-11-04
申请人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
发明人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
IPC分类号： G03F900
CPC分类号： G03F1/32
摘要： A method of manufacturing a binary phase shift photomask. A phase shift layer and a mask layer are sequentially formed over a transparent substrate. The mask layer and the phase shift layer are patterned to form a plurality of first openings and a plurality of second openings that expose a portion of the transparent substrate. The mask layer is patterned to form a layer of mask material around the edges of the first openings. All first openings occupy an area greater than a preset minimum area while all second openings occupy an area greater than the preset minimum area. The mask layer only surrounds the first openings while the phase shift layer surrounds both the first and the second openings.
摘要翻译：一种制造二进制相移光掩模的方法。在透明基板上依次形成相移层和掩模层。图案化掩模层和相移层以形成多个第一开口和暴露透明基板的一部分的多个第二开口。图案化掩模层以在第一开口的边缘周围形成掩模材料层。所有第一开口占据大于预设最小面积的区域，而所有第二开口占据大于预设最小面积的区域。掩模层仅围绕第一开口，而相移层围绕第一和第二开口。

53. 发明授权

US08569845B2 Strained silicon device 有权
标题翻译：应变硅器件
公开(公告)号：US08569845B2
公开(公告)日：2013-10-29
申请号：US11549002
申请日：2006-10-12
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L21/02
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

54. 发明授权

US07504652B2 Phase change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07504652B2
公开(公告)日：2009-03-17
申请号：US11180430
申请日：2005-07-13
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective coating (ARC) film on the bottom electrode film, patterning and etching the ARC film and the bottom electrode film to form a bottom electrode comprising a side edge, and forming a phase change material portion on the ARC film and the bottom insulating layer, wherein the phase change material portion physically contacts the side edge of the bottom electrode. The method further includes forming a top electrode on the phase change material portion, and forming a top electrode contact on the top electrode.
摘要翻译：提供了具有减小的相变容积和较低驱动电流的相变存储器件及其形成方法。该方法包括形成底部绝缘层，该底部绝缘层包括底部电极触点，在底部电极触点上形成底部电极膜，在底部电极膜上形成抗反射涂层（ARC）膜，对ARC膜和底部形成包括侧边缘的底部电极，并且在所述ARC膜和所述底部绝缘层上形成相变材料部分，其中所述相变材料部分物理接触所述底部电极的侧边缘。该方法还包括在相变材料部分上形成顶部电极，以及在顶部电极上形成顶部电极接触。

55. 发明授权

US07462554B2 Method for forming semiconductor device with modified channel compressive stress 有权
标题翻译：用于形成具有改变的通道压应力的半导体器件的方法
公开(公告)号：US07462554B2
公开(公告)日：2008-12-09
申请号：US11219439
申请日：2005-09-02
申请人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Tone-Xuan Chung , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L31/119
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.
摘要翻译：用于形成半导体器件的方法提供在衬底的顶部上形成栅极区域。栅极侧壁衬里形成在栅极区域的相对侧上，侧壁衬里具有接触栅极区域的侧壁和与衬底接触的水平部分的垂直部分。嵌入式间隔件形成在侧壁衬垫的顶部。垫片下方的侧壁衬套从相应的垫片的边缘被拉回预定的距离。通过减小原来形成的间隔物的高度来形成凹进的间隔物。间隔件的高度低于门侧壁衬套的高度，并且侧壁衬套的水平部分的宽度比间隔件的宽度短。减少的间隔物高度降低了设备通道应力。

56. 发明申请

US20080248404A1 Method for Controlling Phase Angle of a Mask by Post-Treatment 有权
标题翻译：通过后处理控制面膜相位角的方法
公开(公告)号：US20080248404A1
公开(公告)日：2008-10-09
申请号：US11697015
申请日：2007-04-05
申请人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
发明人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
IPC分类号： G03F1/00
CPC分类号： G03F1/26 , G03F1/32
摘要： A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask.
摘要翻译：提供了一种用于控制掩模的相位角的方法。形成包括基板和吸收体的掩模。对掩模进行含氮等离子体处理以减小相位角。或者，对掩模进行含氮等离子体处理，然后进行真空紫外线处理，以在掩模上形成钝化层。

57. 发明申请

US20080171419A1 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US20080171419A1
公开(公告)日：2008-07-17
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/76 , H01L21/44
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

58. 发明申请

US20070278541A1 Spacer engineering on CMOS devices 审中-公开
标题翻译： CMOS器件上的间隔工程
公开(公告)号：US20070278541A1
公开(公告)日：2007-12-06
申请号：US11446912
申请日：2006-06-05
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/1083 , H01L29/6656 , H01L29/7842
摘要： A MOS device having a reduced LDD dopant diffusion length and a method for forming the same are provided. The MOS device includes a gate stack over a semiconductor substrate, a spacer liner on a sidewall of the gate stack and having a portion over the semiconductor substrate, and a spacer over the spacer liner. The spacer for a PMOS device preferably has a tensile stress, and the spacer for an NMOS device preferably has a compressive stress.
摘要翻译：提供具有降低的LDD掺杂剂扩散长度的MOS器件及其形成方法。 MOS器件包括在半导体衬底上的栅极堆叠，在栅极堆叠的侧壁上的间隔衬垫，并且具有半导体衬底上的部分，以及间隔衬垫上的间隔物。用于PMOS器件的间隔物优选具有拉伸应力，并且用于NMOS器件的间隔物优选地具有压应力。

59. 发明申请

US20070222035A1 Stress intermedium engineering 审中-公开
标题翻译：应力中介工程
公开(公告)号：US20070222035A1
公开(公告)日：2007-09-27
申请号：US11387601
申请日：2006-03-23
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A stressor layer is formed over the transistor. Embodiments include an intermedium layer between the stressor layer and a portion of the transistor. In an embodiment, the intermedium comprises a layer formed between the stressor layer and the gate electrode sidewall spacers. In another embodiment, the intermedium comprises a silicided portion of the substrate formed over the LDS/LDD regions. A transistor that includes the intermedium and, stressor layer has a vertically oriented stress within the channel region. The vertically oriented stress is tensile in a PMOS transistor and compressive in an NMOS transistor.
摘要翻译：本发明的实施例提供了用于形成应变MOS晶体管的结构和方法。在晶体管上方形成应力层。实施例包括应力层与晶体管的一部分之间的中间层。在一个实施例中，中间层包括在应力层和栅电极侧壁间隔件之间形成的层。在另一个实施例中，中间层包括在LDS / LDD区上形成的衬底的硅化物部分。包括中间层和应力层的晶体管在沟道区域内具有垂直取向的应力。垂直取向的应力是PMOS晶体管中的拉伸和NMOS晶体管中的压缩。

60. 发明授权

US07265425B2 Semiconductor device employing an extension spacer and a method of forming the same 有权
标题翻译：采用延伸间隔物的半导体装置及其形成方法
公开(公告)号：US07265425B2
公开(公告)日：2007-09-04
申请号：US10989073
申请日：2004-11-15
申请人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76829 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
摘要翻译：形成在半导体衬底上的半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。源极/漏极延伸在电介质衬垫和延伸垫片下面。半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

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