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    • 51. 发明授权
    • Sacrificial feature for corrosion prevention during CMP
    • CMP期间防腐蚀的牺牲特征
    • US06787470B2
    • 2004-09-07
    • US10150300
    • 2002-05-17
    • Chu-Wei HuTsu ShihChen Cheng Chou
    • Chu-Wei HuTsu ShihChen Cheng Chou
    • H01L21302
    • H01L21/7684H01L21/3212Y10S438/959
    • A sacrificial semiconductor feature for preventing corrosion that can result during chemical-mechanical planarization (CMP) is disclosed. A semiconductor device of the invention is fabricated at least in part by performing CMP. The device includes a desired semiconductor feature and a sacrificial semiconductor feature. The desired semiconductor feature may have an unbalanced geometric pattern that includes a metallic line ending in at least one tip. The at least one tip is susceptible to corrosion resulting from performing CMP. The sacrificial semiconductor feature is preferably located off the metallic line of the desired semiconductor feature. The sacrificial semiconductor feature attracts charge induced during CMP that is otherwise attracted by the at least one tip of the desired semiconductor feature. The presence of the sacrificial semiconductor feature thus substantially prevents corrosion of the desired semiconductor feature, including its tip(s).
    • 公开了一种用于防止在化学机械平面化(CMP)期间可能产生的腐蚀的牺牲半导体特征。 至少部分地通过执行CMP来制造本发明的半导体器件。 该器件包括期望的半导体特征和牺牲半导体特征。 期望的半导体特征可以具有不平衡几何图案,其包括终止于至少一个尖端的金属线。 至少一个尖端容易受到执行CMP的腐蚀。 牺牲半导体特征优选地位于期望的半导体特征的金属线之外。 牺牲半导体特征吸引由CMP期望的半导体特征的至少一个尖端吸引的电荷。 因此牺牲半导体特征的存在基本上防止了期望的半导体特征(包括其尖端)的腐蚀。
    • 53. 发明授权
    • Method for forming metal filled semiconductor features to improve a subsequent metal CMP process
    • 用于形成金属填充的半导体特征以改进随后的金属CMP工艺的方法
    • US06599838B1
    • 2003-07-29
    • US10188442
    • 2002-07-02
    • Tsu ShihSung-Ming Jang
    • Tsu ShihSung-Ming Jang
    • H01L214763
    • H01L21/76802H01L21/3212H01L21/76829H01L21/7684
    • A method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process including providing a semiconductor processing surface having a anisotropically etched semiconductor feature formed through a thickness including a second dielectric insulating layer overlying a first dielectric insulating layer, the second dielectric insulating layer having a CMP material removal rate in a CMP process less than about ½ of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature with a metal to form a metal filled semiconductor feature; and, planarizing according to the CMP process excess material including the metal overlying the second dielectric insulating layer.
    • 一种形成金属填充半导体器件的方法,包括用于改善CMP抛光工艺的低介电常数CMP抛光停止层,包括提供具有各向异性蚀刻半导体特征的半导体处理表面,所述半导体处理表面通过厚度形成,所​​述厚度包括覆盖在第一电介质 绝缘层,所述第二介电绝缘层在CMP工艺中具有小于CMP工艺中第一介电绝缘层的CMP材料去除速率的约1/2的CMP材料去除速率; 用金属填充各向异性蚀刻的半导体特征以形成金属填充的半导体特征; 并且根据CMP工艺平面化包括覆盖在第二介电绝缘层上的金属的多余材料。
    • 54. 发明授权
    • Method to eliminate post-CMP copper flake defect
    • 消除CMP后铜片缺陷的方法
    • US06544891B1
    • 2003-04-08
    • US09945435
    • 2001-09-04
    • Ying-Ho ChenWen-Chih ChiouTsu ShihSyun-Ming Jang
    • Ying-Ho ChenWen-Chih ChiouTsu ShihSyun-Ming Jang
    • H01L2144
    • H01L21/7684H01L21/76838
    • A method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process is described. A first metal line is provided on an insulating layer overlying a semiconductor substrate. A dielectric stop layer is deposited overlying the first metal line. A dielectric layer is deposited overlying the dielectric stop layer. An opening is etched through the dielectric layer and the dielectric stop layer to the first metal line. A barrier metal layer is deposited over the surface of the dielectric layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and barrier metal layer not within the opening are polished away wherein after a time period, copper flakes form on the surface of the copper and dielectric layers. The copper layer and the dielectric layer are alloyed whereby the copper layer is stabilized and the copper flakes are removed to complete copper damascene metallization in the fabrication of an integrated circuit.
    • 描述了通过退火工艺消除铜剥落和金属桥接问题的铜金属化方法。 第一金属线设置在覆盖在半导体衬底上的绝缘层上。 沉积在第一金属线上的电介质停止层。 介电层沉积在介电阻挡层上。 通过介电层和电介质停止层蚀刻开口到第一金属线。 阻挡金属层沉积在电介质层的表面上并且在开口内。 在阻挡金属层的表面上沉积铜层。 不在开口内的铜层和阻挡金属层被抛光,其中在一段时间之后,在铜和电介质层的表面上形成铜片。 将铜层和电介质层合金化,由此铜层稳定,并且在制造集成电路中去除铜片以完成铜镶嵌金属化。
    • 56. 发明授权
    • Polishing platen equipped with guard ring for chemical mechanical polishing
    • 抛光台装有防护环,用于化学机械抛光
    • US06443810B1
    • 2002-09-03
    • US09547256
    • 2000-04-11
    • Tsu Shih
    • Tsu Shih
    • B24B100
    • B24B37/16B24D9/08
    • A polishing pad platen that is equipped with a guard ring, or a slurry retaining collar, used in chemical mechanical polishing (CMP) for conserving usage of polishing slurry is described. A method for conserving slurry solution during a CMP process is further described. In the novel polishing pad platen, a guard ring is mounted to the platen by sealiningly engaging an outer periphery of the platen for preventing spilling out of slurry solution during a polishing operation. The guard ring is mounted to slidingly engage the platen in such a way that the ring may be lowered to be completely out of the way during a pad condition process in which the spinning out of a pad conditioning solution from a top surface of the polishing pad is necessary.
    • 描述了用于化学机械抛光(CMP)中用于保存抛光浆料的使用的抛光垫板,其配备有保护环或浆料保持环。 进一步描述了在CMP工艺期间保存浆液的方法。 在新型抛光垫台板中,通过密封地接合压板的外周而将保护环安装到压板上,以防止在抛光操作期间溢出浆液。 保护环被安装成滑动地接合压板,使得环可以在衬垫状态过程中完全脱落,其中从抛光垫的顶表面旋出焊盘调节溶液 是必要的。
    • 57. 发明授权
    • Slurry dispenser having multiple adjustable nozzles
    • 浆料分配器具有多个可调喷嘴
    • US06398627B1
    • 2002-06-04
    • US09815427
    • 2001-03-22
    • Wen-Chih ChiouYing-Ho ChenTsu ShihSyun-Ming Jang
    • Wen-Chih ChiouYing-Ho ChenTsu ShihSyun-Ming Jang
    • B24B900
    • B24B37/04B24B57/02
    • A slurry dispensing unit for a chemical mechanical polishing apparatus equipped with multiple slurry dispensing nozzles is disclosed. The slurry dispensing unit is constructed by a dispenser body that has a delivery conduit, a return conduit and a U-shape conduit connected in fluid communication therein between for flowing continuously a slurry solution therethrough and a plurality of nozzles integrally connected to and in fluid communication with a fluid passageway in the delivery conduit for dispensing a slurry solution. The multiple slurry dispensing nozzles may either have a fixed opening or adjustable openings by utilizing a flow control valve at each nozzle opening.
    • 公开了一种用于配备有多个浆料分配喷嘴的化学机械抛光设备的浆料分配单元。 浆料分配单元由分配器主体构成,分配器主体具有输送管道,回流管道和连接在其中的流体连通的U形管道,用于连续地流动通过其中的浆液;以及多个喷嘴,其一体地连接到流体连通 在输送管道中具有用于分配浆液的流体通道。 多个浆料分配喷嘴可以通过在每个喷嘴开口处利用流量控制阀来具有固定的开口或可调节的开口。
    • 58. 发明授权
    • Segmented box-in-box for improving back end overlay measurement
    • 分段盒装盒,用于改进后端重叠测量
    • US6118185A
    • 2000-09-12
    • US262303
    • 1999-03-04
    • Jeng-Horng ChenTsu Shih
    • Jeng-Horng ChenTsu Shih
    • G03F7/20H01L23/544H01L21/46H01L21/76H01L21/78H01L23/58
    • G03F7/70633Y10S438/975
    • An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.
    • 通过从包括从沟槽的底部向上突出的多个同心脊组成的分段沟槽形成外盒已经实现了箱内叠加测量方法的改进。 当分段的沟槽已经用钨(或类似的金属)过量填充时,使用回蚀或化学去除多余的金属。 机械 抛光作为平面化技术。 由于脊的存在,当内盒(将从第一层沉积的第二层蚀刻时)位于其内部时,沟槽(即外盒)变得可再现地容易看到。 此外,现在很大程度上消除了外箱在关键位置的破坏(通常在现有技术中看到)的倾向。
    • 59. 发明授权
    • Alignment method for used in chemical mechanical polishing process
    • 用于化学机械抛光工艺的对准方法
    • US5933744A
    • 1999-08-03
    • US54302
    • 1998-04-02
    • Jeng-Horng ChenTsu ShihJui-Yu ChangChung-Long Chang
    • Jeng-Horng ChenTsu ShihJui-Yu ChangChung-Long Chang
    • H01L21/3105H01L23/544H01L21/465H01L21/76
    • H01L23/544H01L21/31053H01L2223/54453H01L2924/0002Y10S438/975
    • A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.
    • 用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。 第一介电层沉积在晶片上用于隔离。 然后,使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。 在第一电介质层中形成第一导电插塞。 接下来,在第一电介质层的表面和钨插塞上形成第一导电层。 因此,第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。 接下来,在第二导电层的表面上形成第二非零对准标记图案,并与第二导电插塞对准。 通过重复上述方法,将在第一非零对准标记图案上形成奇数非零对准标记图案,并且甚至在第二非零对准标记图案上形成非零对准标记图案。 因此,本发明节省空间,将非零对准标记放置在多层互连和平面化处理中。