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51. 发明授权

US08706785B2 Communication system with signal processing mechanism and method of operation thereof 有权
标题翻译：具有信号处理机制的通信系统及其操作方法
公开(公告)号：US08706785B2
公开(公告)日：2014-04-22
申请号：US13163661
申请日：2011-06-17
申请人： Vladislav Sorokine , Jungwon Lee , Sungsoo Kim , Inyup Kang
发明人： Vladislav Sorokine , Jungwon Lee , Sungsoo Kim , Inyup Kang
IPC分类号： G06F17/10
CPC分类号： H04L25/0216 , H04L25/022 , H04L27/2647 , H04L2025/03414
摘要： A method of operation of a communication system includes: generating a filter impulse response and a filter time-domain data with a shortening filter; generating a filter frequency response based on the filter impulse response with a filter frequency response calculator; generating a filter frequency-domain data based on the filter time-domain data with a first process unit; and generating a raw channel impulse response with a filter frequency removal unit for removing the filter frequency response from the filter frequency-domain data.
摘要翻译：一种通信系统的操作方法包括：利用缩短滤波器产生滤波器脉冲响应和滤波器时域数据; 利用滤波器频率响应计算器产生基于滤波器脉冲响应的滤波器频率响应; 使用第一处理单元基于所述滤波器时域数据生成滤波器频域数据; 以及用滤波器频率去除单元产生原始信道脉冲响应，以从滤波器频域数据中去除滤波器频率响应。

52. 发明授权

US08626099B2 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US08626099B2
公开(公告)日：2014-01-07
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B1/06
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

53. 发明授权

US08615212B2 Direct conversion receiver architecture 有权
公开(公告)号：US08615212B2
公开(公告)日：2013-12-24
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

54. 发明申请

US20130196670A1 MOBILE COMMUNICATION SYSTEM WITH DEVICE HANDOVER AND METHOD OF OPERATION THEREOF 有权
标题翻译：具有设备切换的移动通信系统及其操作方法
公开(公告)号：US20130196670A1
公开(公告)日：2013-08-01
申请号：US13360547
申请日：2012-01-27
申请人： Sungsoo Kim , Inyup Kang , Jungwon Lee
发明人： Sungsoo Kim , Inyup Kang , Jungwon Lee
IPC分类号： H04W36/00
CPC分类号： H04W36/32 , G01S11/06 , H04W36/0083 , H04W64/006
摘要： A method of operation of a mobile communication system includes: receiving a base carrier frequency signal from a cell tower location; generating a power spectral density from the base carrier frequency signal; measuring a Rician K factor from the power spectral density; estimating a line-of-sight Doppler frequency based on the base carrier frequency signal; determining the cell tower location based on the Rician K factor; and activating a handover decision handler based on the cell tower location.
摘要翻译：移动通信系统的操作方法包括：从小区塔位置接收基载波频率信号; 从所述基本载波频率信号产生功率谱密度; 从功率谱密度测量Rician K因子; 基于所述基本载波频率信号估计视线多普勒频率; 基于Rician K因子确定细胞塔位置; 以及基于所述小区塔位置激活切换判定处理器。

55. 发明申请

US20130150053A1 COMMUNICATION SYSTEM WITH ADAPTIVE HANDOVER CONTROLLER AND METHOD OF OPERATION THEREOF 有权
标题翻译：具有自适应切换控制器的通信系统及其操作方法
公开(公告)号：US20130150053A1
公开(公告)日：2013-06-13
申请号：US13315275
申请日：2011-12-08
申请人： Insoo Hwang , Jungwon Lee , Heejin Roh , Inyup Kang
发明人： Insoo Hwang , Jungwon Lee , Heejin Roh , Inyup Kang
IPC分类号： H04W36/00 , H04W36/34
CPC分类号： H04W36/0083
摘要： A method of operation of a communication system includes: estimating a channel; calculating a predicted signal within the channel; evaluating a prediction accuracy of the predicted signal; and adjusting a handoff parameter when the prediction accuracy of the predicted signal is within a threshold range for communicating through a mobile station.
摘要翻译：通信系统的操作方法包括：估计信道; 计算信道内的预测信号; 评估预测信号的预测精度; 以及当所述预测信号的预测精度在用于通过移动台进行通信的阈值范围内时，调整切换参数。

56. 发明申请

US20120051407A1 APPARATUS AND METHODS FOR SAMPLING RATE CONVERSION FOR WIRELESS TRANSCEIVERS 失效
标题翻译：用于无线收发器采样速率转换的装置和方法
公开(公告)号：US20120051407A1
公开(公告)日：2012-03-01
申请号：US13033902
申请日：2011-02-24
申请人： Zhu Ji , Brian Clarke Banister , Inyup Kang
发明人： Zhu Ji , Brian Clarke Banister , Inyup Kang
IPC分类号： H04W24/00 , H04B1/38
CPC分类号： H03H17/0294 , H03H17/0642
摘要： Disclosed are methods and apparatus for sampling rate conversion in a wireless transceiver. The methods and apparatus achieve agile setting of sampling rates or resampling by adaptively setting a sampling rate of a signal based on at least one performance requirement of the transceiver. In particular, the methods and apparatus perform sampling of an input signal at a first sampling rate to gain one or more input signal samples. The input signal samples are then filtered using parallel or polyphase filtering operating at a second sampling rate lower than the first sampling rate. The filtered samples are then interpolated at the second sampling rate to achieve resampling of the input signal. Polyphase filtering affords an effectively high input sampling rate for good spectrum image rejection, while allowing the second sampling rate to be effectively much lower than the first rate, thereby reducing the complexity of multiplier operations for interpolation.
摘要翻译：公开了无线收发器中采样率转换的方法和装置。方法和装置通过基于收发器的至少一个性能要求自适应地设置信号的采样速率来实现采样率的敏捷设置或重新采样。特别地，方法和装置以第一采样率对输入信号进行采样，以获得一个或多个输入信号采样。然后使用以低于第一采样速率的第二采样率运行的并行或多相滤波来过滤输入信号采样。然后以第二采样率对经滤波的采样进行内插，以实现输入信号的重新采样。多相滤波提供了有效的高输入采样率以获得良好的频谱图像抑制，同时允许第二采样率实际上远低于第一速率，从而降低了用于插值的乘法器操作的复杂度。

57. 发明授权

US08064556B2 Fractionally-spaced equalizers for spread spectrum wireless communication 有权
标题翻译：用于扩频无线通信的分数间隔均衡器
公开(公告)号：US08064556B2
公开(公告)日：2011-11-22
申请号：US11502178
申请日：2006-08-09
申请人： Parvathanathan Subrahmanya , Inyup Kang , Jia Fei , Rajesh Sundaresan
发明人： Parvathanathan Subrahmanya , Inyup Kang , Jia Fei , Rajesh Sundaresan
IPC分类号： H04B1/10
CPC分类号： H04B1/71057 , H04B7/0669 , H04B7/0673 , H04B7/0845 , H04L25/03044 , H04L25/03292 , H04L2025/03509
摘要： This disclosure describes equalization techniques for spread spectrum wireless communication. The techniques may involve estimating a channel impulse response, estimating channel variance, and selecting filter coefficients for an equalizer based on the estimated channel impulse response and the estimated channel variance. Moreover, in accordance with this disclosure, the channel variance estimation involves estimation of two or more co-variances for different received samples. Importantly, the equalizer is “fractionally spaced,” which means that the equalizer defines fractional filtering coefficients (filter taps), unlike conventional equalizers that presume that filter coefficients are defined at integer chip spacing. The techniques can allow the equalizer to account for antenna diversity, such as receive diversity, transmit diversity, or possibly both.
摘要翻译：本公开描述了用于扩频无线通信的均衡技术。这些技术可以包括基于所估计的信道脉冲响应和所估计的信道方差估计信道脉冲响应，估计信道方差，以及为均衡器选择滤波器系数。此外，根据本公开，信道方差估计涉及对于不同接收样本的两个或多个协方差的估计。重要的是，均衡器是“分数间隔”的，这意味着均衡器定义了分数滤波系数（滤波器抽头），不同于传统的均衡器，假设滤波器系数是以整数芯片间隔定义的。这些技术可以允许均衡器考虑天线分集，例如接收分集，发射分集，或者可能两者。

58. 发明授权

US07929509B2 Reduced cell acquisition time 有权
标题翻译：减少细胞获取时间
公开(公告)号：US07929509B2
公开(公告)日：2011-04-19
申请号：US11126526
申请日：2005-05-10
申请人： Inyup Kang
发明人： Inyup Kang
IPC分类号： H04B7/216
CPC分类号： H04B1/7083 , H04B1/70735
摘要： A method and apparatus for reduced acquisition time are disclosed. In one embodiment, such as in a W-CDMA system, a receiver receives one or more signals from remote stations, each signal comprising a scrambling code associated with one of a plurality of code groups, each code group identified by a unique series of a synchronization codes. A searcher identifies a subset of first synchronization codes, and a processor selects one or more hypotheses in response to the received subset. The searcher may then perform searching for a scrambling code in accordance with the one or more hypotheses. The scrambling code search may be performed in parallel with continued synchronization code searching. Various other embodiments are also disclosed.
摘要翻译：公开了一种缩短采集时间的方法和装置。在一个实施例中，例如在W-CDMA系统中，接收机从远程站接收一个或多个信号，每个信号包括与多个代码组中的一个相关联的扰码，每个代码组由唯一的一系列同步码搜索者识别第一同步码的子集，并且处理器响应于所接收的子集选择一个或多个假设。然后，搜索者可以根据一个或多个假设执行搜索扰码。可以与继续的同步码搜索并行地执行扰码搜索。还公开了各种其它实施例。

59. 发明申请

US20110044380A1 DYNAMICALLY CHANGING A TRANSMITTER SAMPLING FREQUENCY FOR A DIGITAL-TO-ANALOG CONVERTER (DAC) TO REDUCE INTERFERENCE FROM DAC IMAGES 有权
标题翻译：动态更改用于数字模拟转换器（DAC）的发射机采样频率，以减少DAC图像的干扰
公开(公告)号：US20110044380A1
公开(公告)日：2011-02-24
申请号：US12823668
申请日：2010-06-25
申请人： Thomas D. Marra , Soon-Seng Lau , Inyup Kang , Arash Mirbagheri
发明人： Thomas D. Marra , Soon-Seng Lau , Inyup Kang , Arash Mirbagheri
IPC分类号： H04B15/00
CPC分类号： H04B1/525 , H03M1/661 , H04B1/0475
摘要： A method for interference reduction is described. The method is implemented in a wireless device. It is determined that a page is going to be received via a secondary receiver. It is also determined that a digital-to-analog converter (DAC) image from a transmitter will cause interference with the secondary receiver when the page is received. A sampling frequency of the DAC for the transmitter is changed so that there are not any DAC images from the transmitter that will cause interference with the secondary receiver.
摘要翻译：描述了一种减少干扰的方法。该方法在无线设备中实现。确定将通过次级接收器接收页面。还确定，当接收到页面时，来自发射器的数模转换器（DAC）图像将引起与次级接收机的干扰。改变发射机的DAC的采样频率，使得没有来自发射机的任何DAC图像将导致与次要接收机的干扰。

60. 发明申请

US20100183096A1 EFFICIENT MULTI-SYMBOL DEINTERLEAVER 有权
标题翻译：有效的多符号检测器
公开(公告)号：US20100183096A1
公开(公告)日：2010-07-22
申请号：US12717742
申请日：2010-03-04
申请人： Hanfang Pan , Inyup Kang , James Krysl
发明人： Hanfang Pan , Inyup Kang , James Krysl
IPC分类号： H04L27/22 , G06F11/00 , H03M13/03
CPC分类号： H03M13/2764 , H03M13/2703
摘要： Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.
摘要翻译：本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。在一个方面，部署多个存储体以根据存储模式接收并同时存储多个值，诸如从调制星座确定的软判决值。在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。还提出了各种其他方面。这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。

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