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51. 发明申请

US20120082171A1 SINGLE CHIP PROTOCOL CONVERTER 有权
标题翻译：单芯片协议转换器
公开(公告)号：US20120082171A1
公开(公告)日：2012-04-05
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04L12/00
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

52. 发明授权

US08135917B2 Method and apparatus for filtering snoop requests using stream registers 有权
标题翻译：使用流寄存器对窥探请求进行过滤的方法和装置
公开(公告)号：US08135917B2
公开(公告)日：2012-03-13
申请号：US12137325
申请日：2008-06-11
申请人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0822 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联的本地高速缓冲存储器。窥探过滤设备与每个处理单元相关联并且包括至少一个基于流寄存器集合和相关流寄存器比较逻辑的使用实现过滤方法的窥探过滤器原语。从多个流寄存器组中，至少一个流寄存器组是有效的，并且至少一个流寄存器集合在任何时间点被标记为历史。另外，监听滤波器块可操作地与高速缓存包检测逻辑耦合，从而将活动流寄存器集合的内容切换到在高速缓存环绕条件检测时设置的历史流寄存器，并且至少一个活动流寄存器集合的内容被复位。每个滤波器基元实现流寄存器比较逻辑，其确定接收的窥探请求是否被转发到处理器或丢弃。

53. 发明授权

US08127078B2 High performance unaligned cache access 有权
标题翻译：高性能未对齐缓存访问
公开(公告)号：US08127078B2
公开(公告)日：2012-02-28
申请号：US12572416
申请日：2009-10-02
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0886
摘要： A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache line, and a second cache array coupled to an alignment unit is configured to output a second cache entry associated with the alignment cache line. The alignment unit coupled to the address decoder selects either the target cache line or a neighbor cache line proximate the target cache line as an alignment cache line output. Selection of either the target cache line or a neighbor cache line is based on an alignment bit in the memory address. A tag array cache is split into even and odd cache lines tags, and provides one or two tags for every cache access.
摘要翻译：一种高速缓冲存储器件及其操作方法。高速缓冲存储器设备的一个实施例包括解码存储器地址并选择目标高速缓存行的地址译码器。第一高速缓存阵列被配置为输出与目标高速缓存行相关联的第一高速缓存条目，并且耦合到对准单元的第二高速缓存阵列被配置为输出与对准高速缓存行相关联的第二高速缓存条目。耦合到地址解码器的对准单元选择目标高速缓存线或邻近目标高速缓存行的相邻高速缓存行作为对准高速缓存行输出。目标高速缓存行或相邻高速缓存行的选择基于存储器地址中的对齐位。标签数组高速缓存分为偶数和奇数缓存行标签，并为每个高速缓存访问提供一个或两个标签。

54. 发明申请

US20110247003A1 Predictive Dynamic System Scheduling 有权
标题翻译：预测动态系统调度
公开(公告)号：US20110247003A1
公开(公告)日：2011-10-06
申请号：US12751288
申请日：2010-03-31
申请人： Liana L. Fong , Valentina Salapura , Seetharami Seelam
发明人： Liana L. Fong , Valentina Salapura , Seetharami Seelam
IPC分类号： G06F9/46
CPC分类号： G06F9/5061
摘要： Resources of a partitionable computer system are partitioned into at least first and second partitions, in accordance with a first or second mode of operation of the partitionable computer system. The system is run in the first or second mode, partitioned in accordance with the partitioning step. Periodically, it is determined whether the computer system should be switched from one mode to the other mode. If so, the computer system is run in the other mode, partitioned in accordance with the other mode. The first and second modes of operation are defined in accordance with historical observations of the partitionable computer system. The periodic determination is carried out based on predictions in accordance with the historical observations.
摘要翻译：根据可分割计算机系统的第一或第二操作模式，可分区计算机系统的资源被划分为至少第一和第二分区。系统以第一或第二模式运行，根据分区步骤进行分区。定期地，确定计算机系统是否应该从一种模式切换到另一种模式。如果是这样，则计算机系统以其他模式运行，根据其他模式进行分区。第一和第二操作模式根据可分区计算机系统的历史观察来定义。根据历史观察的预测进行周期性测定。

55. 发明申请

US20110247002A1 Dynamic System Scheduling 有权
标题翻译：动态系统调度
公开(公告)号：US20110247002A1
公开(公告)日：2011-10-06
申请号：US12751251
申请日：2010-03-31
申请人： Valentina Salapura , Seetharami Seelam
发明人： Valentina Salapura , Seetharami Seelam
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/5061 , Y02D10/22 , Y02D10/36
摘要： Resources of a partitionable computer system are partitioned into: (i) a first partition for first jobs, the first jobs being at least one of small and short running; and (ii) a second partition for second jobs, the second jobs being at least one of large and long running. The computer system is run as partitioned in the partitioning step and the partitioning is periodically re-evaluated against at least one threshold for at least one of the partitions. If the periodic re-evaluation suggests that one of the first and second partitions is underutilized, the resources of the partitionable computer system are dynamically re-partitioned to reassign at least some of the resources of the partitionable computer system from the underutilized one of the first and second partitions to another one of the first and second partitions
摘要翻译：可分区计算机系统的资源被划分为：（i）用于第一作业的第一分区，第一作业是小和短运行中的至少一个; 和（ii）用于第二作业的第二分区，所述第二作业是大的和长的运行中的至少一个。计算机系统在分区步骤中分区运行，并且针对至少一个分区的至少一个阈值周期性地重新评估分区。如果周期性重新评估表明第一和第二分区中的一个未充分利用，则可分区计算机系统的资源被动态地重新划分，以将可分区计算机系统的至少一些资源从第一以及第二分区到第一和第二分区中的另一个分区

56. 发明授权

US08015364B2 Method and apparatus for filtering snoop requests using a scoreboard 有权
标题翻译：使用记分板过滤窥探请求的方法和装置
公开(公告)号：US08015364B2
公开(公告)日：2011-09-06
申请号：US12129289
申请日：2008-05-29
申请人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
摘要翻译：用于实现窥探高速缓存一致性的装置，其本地地减少呈现给多处理器系统中的每个缓存的窥探请求的数量。与单个处理器相关联的窥探过滤器装置包括一个或多个“记分板”数据结构，其进行窥探确定，即，来自另一个处理器的每个窥探请求，以确定请求是否被转发到处理器或被丢弃。至少一个记分牌是活跃的，并且至少一个记分牌被确定为在任何时间点的历史。队列的窥探确定表示一个条目可能在缓存中，但不表示其实际居住状态。此外，实现记分板数据结构的窥探过滤器块与高速缓存包检测逻辑装置可操作地耦合，由此在检测到缓存包装条件时，将活动记分板的内容复制到历史记分板中，并且至少一个活动记分板重置。

57. 发明申请

US20110173399A1 DISTRIBUTED PARALLEL MESSAGING FOR MULTIPROCESSOR SYSTEMS 失效
标题翻译：用于多处理器系统的分布式并行消息传递
公开(公告)号：US20110173399A1
公开(公告)日：2011-07-14
申请号：US12693972
申请日：2010-01-26
申请人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/16 , G06F12/02 , G06F15/173 , G06F15/76 , G06F9/06
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.
摘要翻译：一种并行计算系统中分布式并行消息传递的方法和装置。该装置在多处理器网络的每个节点处包括多个注入消息传递引擎单元和接收消息传递引擎单元，每个实现一个DMA引擎，并且每个支持同时支持来自网络的多个分组注入和多个接收。消息接收单元（MU）的接收侧包括能够将从网络接收到的分组的数据写入存储器系统的切换接口。消息传送单元的发送侧包括用于在将分组注入网络时从存储器系统读取的切换接口。

58. 发明授权

US07620756B2 Method and apparatus for updating wide storage array over a narrow bus 有权
标题翻译：用于在窄总线上更新宽存储阵列的方法和装置
公开(公告)号：US07620756B2
公开(公告)日：2009-11-17
申请号：US11507306
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m
摘要翻译：一种用于从窄总线（m位，其中m

59. 发明申请

US20090059955A1 SINGLE CHIP PROTOCOL CONVERTER 失效
标题翻译：单芯片协议转换器
公开(公告)号：US20090059955A1
公开(公告)日：2009-03-05
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/22
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

60. 发明授权

US07477644B2 Method and system of efficient packet reordering 失效
标题翻译：高效数据包重排序方法及系统
公开(公告)号：US07477644B2
公开(公告)日：2009-01-13
申请号：US10604557
申请日：2003-07-30
申请人： Christos J Georgiou , Valentina Salapura
发明人： Christos J Georgiou , Valentina Salapura
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

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