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51. 发明申请

US20070196989A1 Semiconductor device with strained transistors and its manufacture 审中-公开
标题翻译：具有应变晶体管的半导体器件及其制造
公开(公告)号：US20070196989A1
公开(公告)日：2007-08-23
申请号：US11471559
申请日：2006-06-21
申请人： Young Kim , Yosuke Shimamune
发明人： Young Kim , Yosuke Shimamune
IPC分类号： H01L21/336
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.
摘要翻译：半导体器件具有：由第一半导体材料制成的半导体衬底; n型沟道场效应晶体管，其形成在所述半导体衬底中并且具有由与所述第一半导体材料不同的第二半导体材料制成的n型源/漏区; 以及形成在所述半导体衬底中并具有由与所述第一半导体材料不同的第三半导体材料制成的p型源极/漏极区的p沟道场效应晶体管，其中所述第二和第三半导体材料是不同的材料。具有n沟道晶体管和p沟道晶体管的半导体器件通过利用应力来提高性能。

52. 发明授权

US06621145B2 Semiconductor device having a metal-semiconductor junction with a reduced contact resistance 失效
标题翻译：具有具有降低的接触电阻的金属 - 半导体结的半导体器件
公开(公告)号：US06621145B2
公开(公告)日：2003-09-16
申请号：US09866695
申请日：2001-05-30
申请人： Junichi Murota , Yosuke Shimamune , Masao Sakuraba , Takashi Matsuura
发明人： Junichi Murota , Yosuke Shimamune , Masao Sakuraba , Takashi Matsuura
IPC分类号： H01L29167
CPC分类号： H01L21/02576 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/28525 , H01L21/28562 , H01L29/456
摘要： A metal-semiconductor junction comprises a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.
摘要翻译：金属 - 半导体结包括布线金属层和半导体层。为了降低结的接触电阻，在半导体层的近表面部分设置掺杂有n型或p型杂质且具有1021cm-3以上的高载流子浓度的区域与金属层相比为10nm以下，高载流子浓度区域由n型或p型杂质层和IV族半导体层构成，这些层通过例如气相成长。

53. 发明申请

US20130210207A1 FABRICATION METHOD OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF DYNAMIC THRESHOLD TRANSISTOR 有权
标题翻译：半导体器件的制造方法和动态阈值晶体管的制造方法
公开(公告)号：US20130210207A1
公开(公告)日：2013-08-15
申请号：US13552274
申请日：2012-07-18
申请人： Masahiro Fukuda , Eiji Yoshida , Yosuke Shimamune
发明人： Masahiro Fukuda , Eiji Yoshida , Yosuke Shimamune
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1207 , H01L29/0653 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/783 , H01L29/7848
摘要： A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
摘要翻译：一种方法包括：除硅衬底部分之外，蚀刻硅衬底，在其上形成沟道区以在硅衬底部分的第一侧和第二侧分别形成第一和第二沟槽; 通过外延生长具有对硅蚀刻选择性的半导体层和另外的硅层来填充第一和第二沟槽; 通过选择性蚀刻工艺去除半导体层选择性，以在衬底部分的第一侧和第二侧分别在硅层下形成空隙; 至少部分地用掩埋绝缘膜掩埋空隙; 在所述硅衬底部分上形成栅极绝缘膜和栅电极; 以及在所述硅衬底部分的第一侧的所述硅层中形成源极区域以及在所述硅衬底部分的第二侧处形成漏极区域。

54. 发明授权

US08455324B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08455324B2
公开(公告)日：2013-06-04
申请号：US12572702
申请日：2009-10-02
申请人： Masahiro Fukuda , Yosuke Shimamune
发明人： Masahiro Fukuda , Yosuke Shimamune
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7833
摘要： A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成栅极绝缘膜和栅电极，通过干蚀刻在栅电极两侧的第一半导体衬底中形成第一凹槽，通过去除底部和第一凹部的侧壁，并且在第二凹部中形成半导体层。

55. 发明授权

US08283226B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08283226B2
公开(公告)日：2012-10-09
申请号：US12690484
申请日：2010-01-20
申请人： Masahiro Fukuda , Yosuke Shimamune , Yuka Kase
发明人： Masahiro Fukuda , Yosuke Shimamune , Yuka Kase
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7843 , H01L29/7848
摘要： A method of manufacturing a semiconductor device includes forming a first cap film over gate electrodes formed in a first active region and a second active region, etching the first cap film over the first active region, forming a second cap film over the gate electrodes formed in the first active region and the second active region, etching the second cap film over the first active region, etching the first active region using the gate electrodes to form concave portions in the first active region, and embedding a semiconductor material in the concave portions.
摘要翻译：一种制造半导体器件的方法包括在形成于第一有源区和第二有源区的栅电极上形成第一盖膜，在第一有源区上蚀刻第一盖膜，在形成于栅电极的栅电极上形成第二帽膜第一有源区和第二有源区，在第一有源区上蚀刻第二覆盖膜，使用栅电极蚀刻第一有源区，以在第一有源区中形成凹部，并将半导体材料埋入凹部。

56. 发明授权

US08232191B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08232191B2
公开(公告)日：2012-07-31
申请号：US12855897
申请日：2010-08-13
申请人： Masahiro Fukuda , Yosuke Shimamune
发明人： Masahiro Fukuda , Yosuke Shimamune
IPC分类号： H01L21/44
CPC分类号： H01L21/823814 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02502 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/823807 , H01L29/165 , H01L29/66636 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.
摘要翻译：一种制造半导体器件的方法，包括在Si衬底上形成栅极绝缘膜和栅电极; 在栅电极的两侧在Si衬底中形成凹陷; 在所述凹部中形成包括Ge的第一Si层; 在所述第一Si层上形成中间层; 在所述中间层上形成包括Ge的第二Si层; 其中所述中间层由包含Ge的Si或Si构成，并且所述中间层的Ge浓度小于所述第一Si层的Ge浓度和所述第二Si层的Ge浓度。

57. 发明授权

US07679147B2 Semiconductor device fabricated by selective epitaxial growth method 有权
标题翻译：通过选择性外延生长法制造的半导体器件
公开(公告)号：US07679147B2
公开(公告)日：2010-03-16
申请号：US12230373
申请日：2008-08-28
申请人： Masahiro Fukuda , Yosuke Shimamune , Masaaki Koizuka , Katsuaki Ookoshi
发明人： Masahiro Fukuda , Yosuke Shimamune , Masaaki Koizuka , Katsuaki Ookoshi
IPC分类号： H01L47/00
CPC分类号： H01L29/7833 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
摘要翻译：提高外延生长中的选择性的半导体器件。提供了一种半导体器件，其包括形成在作为半导体衬底的Si衬底上的栅电极，其间具有栅极绝缘膜，并且在栅电极的侧面上形成含有卤素元素的绝缘层。利用该半导体器件，当在Si衬底上形成SiGe层时，在栅电极的侧面上形成含有卤素元素的氮化硅膜。因此，SiGe层以高选择性外延生长在Si衬底上。结果，抑制了在例如栅电极和源极/漏极区域之间流动的截止状态的漏电流，并且建立了适合于实际批量生产的制造工艺。

58. 发明授权

US07446394B2 Semiconductor device fabricated by selective epitaxial growth method 有权
标题翻译：通过选择性外延生长法制造的半导体器件
公开(公告)号：US07446394B2
公开(公告)日：2008-11-04
申请号：US11717205
申请日：2007-03-13
申请人： Masahiro Fukuda , Yosuke Shimamune , Masaaki Koizuka , Katsuaki Ookoshi
发明人： Masahiro Fukuda , Yosuke Shimamune , Masaaki Koizuka , Katsuaki Ookoshi
IPC分类号： H01L23/58 , H01L21/20 , H01L21/471
CPC分类号： H01L29/7833 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
摘要翻译：提高外延生长中的选择性的半导体器件。提供了一种半导体器件，其包括形成在作为半导体衬底的Si衬底上的栅电极，其间具有栅极绝缘膜，并且在栅电极的侧面上形成并包含卤素元素的绝缘层。利用该半导体器件，当在Si衬底上形成SiGe层时，在栅电极的侧面上形成含有卤素元素的氮化硅膜。因此，SiGe层以高选择性外延生长在Si衬底上。结果，抑制了在例如栅电极和源极/漏极区域之间流动的截止状态的漏电流，并且建立了适合于实际批量生产的制造工艺。

59. 发明申请

US20060281288A1 Semiconductor device fabrication method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20060281288A1
公开(公告)日：2006-12-14
申请号：US11220865
申请日：2005-09-08
申请人： Kazuo Kawamura , Yosuke Shimamune
发明人： Kazuo Kawamura , Yosuke Shimamune
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28525 , H01L21/76829 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The semiconductor device fabrication method comprising the step of forming a gate electrode 54p on a semiconductor substrate 34; the step of forming a source/drain diffused layer 64p in the semiconductor substrate 34 on both sides of the gate electrode 54p; the step of burying a silicon germanium layer 100b in the source/drain diffused layer 64p; the step of forming an amorphous layer at an upper part of the silicon germanium layer 101; the step of forming a nickel film 66 on the amorphous layer 101; and the step of making thermal processing to react the nickel film 66 and the amorphous layer 101 with each other to form a silicide film 102b on the silicon germanium layer 100b. Because of no crystal boundaries in the amorphous layer 101 to react with the nickel film 66, the silicidation homogeneously goes on. Because of no crystal faces in the amorphous layer 101, the Ni(Si1-xGex)2 crystals are prevented from being formed in spikes. Thus, even when the silicon germanium layer 100b is silicided by using a thin nickel film 66, the sheet resistance can be low, and the junction leak current can be suppressed.
摘要翻译：半导体器件制造方法包括在半导体衬底34上形成栅电极54 p的步骤; 在栅极电极54 p的两侧在半导体衬底34中形成源极/漏极扩散层64 p的步骤; 在源极/漏极扩散层64 p中埋入硅锗层100b的步骤; 在硅锗层101的上部形成非晶层的步骤; 在非晶层101上形成镍膜66的步骤; 以及使热处理使镍膜66和非晶层101彼此反应以在硅锗层100b上形成硅化物膜102b的步骤。由于非晶层101中没有晶体边界与镍膜66反应，因此硅化物均匀地继续进行。由于在非晶层101中没有晶面，因此可以防止Ni（Si 1-x N 2）x O 2晶体形成于尖峰。因此，即使当通过使用薄的镍膜66硅化硅锗层100b时，薄层电阻也可以低，并且可以抑制结漏电流。

60. 发明申请

US20060138541A1 Semiconductor device and method of manufacturing same 审中-公开
公开(公告)号：US20060138541A1
公开(公告)日：2006-06-29
申请号：US11360775
申请日：2006-02-24
申请人： Shunji Nakamura , Yosuke Shimamune
发明人： Shunji Nakamura , Yosuke Shimamune
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/7842 , H01L29/78621 , H01L29/78639 , H01L29/78687
摘要： A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.

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