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51. 发明授权

US07951673B2 Forming abrupt source drain metal gate transistors 有权
标题翻译：形成突发源极漏极金属栅极晶体管
公开(公告)号：US07951673B2
公开(公告)日：2011-05-31
申请号：US12713432
申请日：2010-02-26
申请人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
发明人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
摘要翻译：栅极结构可以用作掩模以形成源区和漏区。然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。在将沟槽形成衬底的过程中，去除源极漏极区的一部分。然后用外延材料填充衬底，并在其上形成新的栅极结构。结果，可以实现更突然的源极漏极结。

52. 发明授权

US07338873B2 Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
公开(公告)号：US07338873B2
公开(公告)日：2008-03-04
申请号：US11437569
申请日：2006-05-19
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

53. 发明授权

US06972228B2 Method of forming an element of a microelectronic circuit 失效
标题翻译：形成微电子电路元件的方法
公开(公告)号：US06972228B2
公开(公告)日：2005-12-06
申请号：US10387623
申请日：2003-03-12
申请人： Brian S. Doyle , Anand S. Murthy , Robert S. Chau
发明人： Brian S. Doyle , Anand S. Murthy , Robert S. Chau
IPC分类号： H01L21/20 , H01L29/12 , H01S5/34 , H01L21/8242
CPC分类号： H01L29/66795 , B82Y10/00 , B82Y20/00 , H01L21/02381 , H01L21/02387 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L29/125 , H01S5/341
摘要： A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.
摘要翻译：描述了形成微电子电路的元件的方法。牺牲层形成在支撑层的上表面上。牺牲层非常薄而均匀。然后在牺牲层上形成高度限定层，然后牺牲层被蚀刻掉，使得在支撑层的上表面和高度限定层的下表面之间留下明确限定的间隙。然后从成核硅部位通过间隙选择性地生长单晶半导体材料。单晶半导体材料形成具有对应于原始牺牲层的厚度的厚度的单晶层。

54. 发明授权

US09012284B2 Nanowire transistor devices and forming techniques 有权
标题翻译：纳米线晶体管器件及成型技术
公开(公告)号：US09012284B2
公开(公告)日：2015-04-21
申请号：US13560531
申请日：2012-07-27
申请人： Glenn A. Glass , Kelin J. Kuhn , Seiyon Kim , Anand S. Murthy , Daniel B. Aubertine
发明人： Glenn A. Glass , Kelin J. Kuhn , Seiyon Kim , Anand S. Murthy , Daniel B. Aubertine
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/0676 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7855 , H01L29/78696
摘要： Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
摘要翻译：公开了用于定制纳米线晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。根据一个示例性实施例，除去牺牲翅片并用适合于给定应用的任意组合和应变的定制材料堆叠代替。在一种这样的情况下，第一组牺牲散热片中的每一个凹陷或以其它方式移除并被p型层堆叠代替，并且第二组牺牲散热片中的每一个凹进或以其它方式移除，类型层堆栈。 p型层堆栈可以完全独立于n型层堆栈的过程，反之亦然。使用本文提供的技术可实现许多其它电路配置和设备变化。

55. 发明申请

US20140175543A1 CONVERSION OF THIN TRANSISTOR ELEMENTS FROM SILICON TO SILICON GERMANIUM 有权
标题翻译：将硅晶体管元素转换为硅锗
公开(公告)号：US20140175543A1
公开(公告)日：2014-06-26
申请号：US13722801
申请日：2012-12-20
申请人： Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Stephen M. Cea
发明人： Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Stephen M. Cea
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L29/16 , H01L21/823431 , H01L27/0886 , H01L29/0669 , H01L29/1033 , H01L29/785 , H01L29/7853
摘要： Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了与从硅（Si）到硅锗（SiGe）的薄晶体管元件的转换相关联的技术和配置。在一个实施例中，一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底，沟道体包括硅，在沟道本体上形成包含锗的包覆层，并使通道体退火，锗扩散到通道体内。可以描述和/或要求保护其他实施例。

56. 发明授权

US08642413B2 Formation of strain-inducing films using hydrogenated amorphous silicon 有权
标题翻译：使用氢化非晶硅形成应变诱导膜
公开(公告)号：US08642413B2
公开(公告)日：2014-02-04
申请号：US11521850
申请日：2006-09-14
申请人： Anand S. Murthy , Jeffrey L. Armstrong , Dennis G. Hanken
发明人： Anand S. Murthy , Jeffrey L. Armstrong , Dennis G. Hanken
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle sequence involving hydrogenated amorphous silicon, followed by charge carrier dopant and charge-neutral lattice-forming impurity atom implant steps and, finally, a kinetically-driven crystallization process.
摘要翻译：描述形成应变诱导外延膜的方法。在一个实施例中，应变诱导外延膜是包含来自母膜的原子，电荷 - 中性晶格取代原子和电荷 - 载流子掺杂杂质原子的三组分外延膜。在另一个实施例中，应变诱导外延膜通过涉及氢化非晶硅的多次沉积/蚀刻循环序列形成，随后是电荷载流子掺杂剂和电荷 - 中性晶格形成杂质原子注入步骤，最后是动力学驱动的结晶处理。

57. 发明申请

US20140001520A1 CONTACT RESISTANCE REDUCED P-MOS TRANSISTORS EMPLOYING GE-RICH CONTACT LAYER 审中-公开
标题翻译：接触电阻减少的P-MOS晶体管采用GE-RICH接触层
公开(公告)号：US20140001520A1
公开(公告)日：2014-01-02
申请号：US13539200
申请日：2012-06-29
申请人： Glenn A. Glass , Anand S. Murthy
发明人： Glenn A. Glass , Anand S. Murthy
IPC分类号： H01L29/78 , H01L21/336
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
摘要翻译：公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂的锗 - 锡合金层，以显着降低接触电阻。根据本公开，包括平面和非平面晶体管结构（例如，FinFET和纳米线晶体管）都可以显示许多晶体管配置和合适的制造工艺。这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。

58. 发明申请

US20100133595A1 FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS 有权
标题翻译：具有冲击源/漏联结的场效应晶体管结构
公开(公告)号：US20100133595A1
公开(公告)日：2010-06-03
申请号：US12700637
申请日：2010-02-04
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
摘要翻译：体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。凹部包括在栅极结构的一部分下面的横向延伸的区域。这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。替代实施例可以用单导电类型的后填充凹槽来实现。

59. 发明授权

US07494858B2 Transistor with improved tip profile and method of manufacture thereof 有权
标题翻译：具有改进尖端轮廓的晶体管及其制造方法
公开(公告)号：US07494858B2
公开(公告)日：2009-02-24
申请号：US11173660
申请日：2005-06-30
申请人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
发明人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
IPC分类号： H01L21/336
CPC分类号： H01L29/045 , H01L21/30608 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
摘要翻译：实施例是改进的晶体管结构和制造该结构的方法。特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能并且在源极和漏极与硅化物之间的界面处降低接触电阻。

60. 发明申请

US20090011565A1 Field effect transistor structure with abrupt source/drain junctions 有权
标题翻译：具有突发的源极/漏极结的场效应晶体管结构
公开(公告)号：US20090011565A1
公开(公告)日：2009-01-08
申请号：US12231172
申请日：2008-08-28
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
摘要翻译：体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。凹部包括在栅极结构的一部分下面的横向延伸的区域。这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。替代实施例可以用单导电类型的后填充凹槽来实现。

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