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    • 52. 发明公开
    • 반도체 장치의 제조 방법
    • 半导体器件制造方法
    • KR1020140113246A
    • 2014-09-24
    • KR1020130056609
    • 2013-05-20
    • 삼성전자주식회사
    • 김병희김태수박성호박영주정주영
    • H01L21/768H01L21/28
    • H01L21/76816H01L21/31144
    • Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes providing a lower conductor and a first interlayer dielectric formed around the lower conductor, forming a second interlayer dielectric on the first interlayer dielectric and the lower conductor, forming a first hard mask pattern including a first opening part on the second interlayer dielectric, successively forming a planarization layer and a mask layer on the second interlayer dielectric and the first hard mask pattern, forming a second hard mask pattern including a second opening part on the mask layer, allowing the second hard mask pattern to include SiN and forming a mask pattern by patterning the mask layer by using the second hard mask pattern, removing the second hard mask pattern and forming a trench and a via hole in the second interlayer dielectric by using the mask pattern and the first hard mask pattern.
    • 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供下导体和形成在下导体周围的第一层间电介质,在第一层间电介质和下导体上形成第二层间电介质,形成第一硬掩模图案,其包括第一开口部分 所述第二层间电介质,在所述第二层间电介质和所述第一硬掩模图案上依次形成平坦化层和掩模层,在所述掩模层上形成包括第二开口部分的第二硬掩模图案,所述第二硬掩模图案包括 SiN,并且通过使用第二硬掩模图案图案化掩模层并形成掩模图案,通过使用掩模图案和第一硬掩模图案,去除第二硬掩模图案并在第二层间电介质中形成沟槽和通孔。
    • 58. 发明公开
    • 트랜지스터
    • 晶体管
    • KR1020110074355A
    • 2011-06-30
    • KR1020090131292
    • 2009-12-24
    • 삼성전자주식회사
    • 전상훈송이헌김창정박성호
    • H01L29/786
    • H01L29/7869H01L29/78618H01L29/45
    • PURPOSE: A transistor is provided to prevent etching issue, lack of uniformity, and a leakage current by increasing threshold voltage through an insertion layer between a source electrode and a channel layer. CONSTITUTION: In a transistor, a channel layer(C1) including an oxide semiconductor is formed on a substrate(SUB1). A gate electrode(G1) is formed on the channel layer. A source electrode(S1) and a drain electrode(D1) are respectively contacted with both ends of the channel layer. A semiconductor insertion layer(A1) is formed between the source electrode and the channel layer. A potential barrier between the source electrode and the channel layer is increased by the semiconductor insertion layer.
    • 目的:提供晶体管,以通过增加源电极和沟道层之间的插入层的阈值电压来防止蚀刻问题,缺乏均匀性和漏电流。 构成:在晶体管中,在衬底(SUB1)上形成包括氧化物半导体的沟道层(C1)。 在沟道层上形成栅电极(G1)。 源电极(S1)和漏电极(D1)分别与沟道层的两端接触。 在源电极和沟道层之间形成半导体插入层(A1)。 源电极和沟道层之间的势垒由半导体插入层增加。