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51. 发明授权

US08030700B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08030700B2
公开(公告)日：2011-10-04
申请号：US12405544
申请日：2009-03-17
申请人： Wataru Sakamoto
发明人： Wataru Sakamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate and having a plurality of insulator layers and a plurality of conductive layers alternately stacked; a semiconductor layer provided inside a through-hole formed so as to pass through the stacked body and extending in a stacking direction of the insulator layers and the conductive layers; and a charge trap layer provided between the conductive layer and the semiconductor layer. A lower part in the semiconductor layer is narrower than an upper part therein, and at least the lowermost layer in the conductive layers is thinner than the uppermost layer therein.
摘要翻译：半导体存储器件包括：半导体衬底; 设置在所述半导体基板上并具有交替层叠的多个绝缘体层和多个导电层的层叠体; 设置在通孔内的半导体层，其形成为穿过所述层叠体并沿所述绝缘体层和所述导电层的层叠方向延伸; 以及设置在导电层和半导体层之间的电荷陷阱层。半导体层的下部比其上部窄，并且导电层中的至少最下层比其中最上层薄。

52. 发明申请

US20110193151A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110193151A1
公开(公告)日：2011-08-11
申请号：US12821689
申请日：2010-06-23
申请人： Wataru SAKAMOTO
发明人： Wataru SAKAMOTO
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11529 , H01L27/11548 , H01L27/11575 , H01L29/4234
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions, first active regions provided in the first region and each having a first width, second active regions provided in the second region and each having a second width greater than the first width, third active regions provided in the third region and each having a third with greater than the first width. An upper surface of an element isolation layer in the second region is higher than that of an element isolation layer in the first region.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：半导体衬底，包括其中布置有存储单元晶体管的第一区域;第二区域，其中布置提取与存储单元晶体管电连接的字线的电极;以及其中配置有外围晶体管的第三区域，所述半导体衬底包括分隔相邻有源区的元件隔离层，设置在所述第一区域中的每一个具有第一宽度的第一有源区，并且每个具有第一宽度，所述第二有源区设置在所述第二区中，具有大于第一宽度的第二宽度，设置在第三区域中的每一个具有大于第一宽度的第三有效区域。第二区域中的元件隔离层的上表面高于第一区域中的元件隔离层的上表面。

53. 发明申请

US20100019310A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100019310A1
公开(公告)日：2010-01-28
申请号：US12405544
申请日：2009-03-17
申请人： Wataru SAKAMOTO
发明人： Wataru SAKAMOTO
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate and having a plurality of insulator layers and a plurality of conductive layers alternately stacked; a semiconductor layer provided inside a through-hole formed so as to pass through the stacked body and extending in a stacking direction of the insulator layers and the conductive layers; and a charge trap layer provided between the conductive layer and the semiconductor layer. A lower part in the semiconductor layer is narrower than an upper part therein, and at least the lowermost layer in the conductive layers is thinner than the uppermost layer therein.
摘要翻译：半导体存储器件包括：半导体衬底; 设置在所述半导体基板上并具有交替层叠的多个绝缘体层和多个导电层的层叠体; 设置在通孔内的半导体层，其形成为穿过所述层叠体并沿所述绝缘体层和所述导电层的层叠方向延伸; 以及设置在导电层和半导体层之间的电荷陷阱层。半导体层的下部比其上部窄，并且导电层中的至少最下层比其中最上层薄。

54. 发明授权

US06320805B1 Semiconductor device with external pins 失效
标题翻译：具有外部引脚的半导体器件
公开(公告)号：US06320805B1
公开(公告)日：2001-11-20
申请号：US09767135
申请日：2001-01-23
申请人： Shigeru Yamaoka , Wataru Sakamoto
发明人： Shigeru Yamaoka , Wataru Sakamoto
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C29/02
摘要： In a high-speed SDRAM, a contact resistance detecting circuit is provided for detecting a contact resistance value between a socket and an external pin. At the time of testing, the contact resistance detecting circuit compares a current flowing from the socket supplied with a power supply potential through the external pin to a first transistor and a constant current flowing from a line of the power supply potential to a second transistor, and, based on the comparison result, outputs a signal of a level corresponding to the contact resistance value.
摘要翻译：在高速SDRAM中，提供接触电阻检测电路，用于检测插座和外部引脚之间的接触电阻值。在测试时，接触电阻检测电路将从提供有通过外部引脚的电源电位的插座流向第一晶体管的电流和从电源电位线流向第二晶体管的恒定电流进行比较，并且基于比较结果，输出与接触电阻值对应的电平的信号。

55. 发明授权

US06292040B1 Internal clock signal generating circuit having function of generating internal clock signals which are multiplication of an external clock signal 失效
标题翻译：内部时钟信号发生电路具有产生与外部时钟信号相乘的内部时钟信号的功能
公开(公告)号：US06292040B1
公开(公告)日：2001-09-18
申请号：US09047375
申请日：1998-03-25
申请人： Hisashi Iwamoto , Wataru Sakamoto , Naoya Watanabe
发明人： Hisashi Iwamoto , Wataru Sakamoto , Naoya Watanabe
IPC分类号： H03L706
CPC分类号： H03L7/07 , H03K23/544 , H03L7/0814 , H03L7/089 , Y10S331/02
摘要： An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency divider, a phase comparator and a shift register. The selector alternately selects an external clock signal and an internal clock signal output from the delay line and outputs the selected signal to the delay line. The delay line receiving the signal delays the external clock signal, and delays the internal clock signal output from itself. The 2-frequency divider divides frequency of the internal clock signal by 2. Phase comparator compares phases of the external clock signal and the output signal from the 2-frequency divider. Delay time of the delay line is adjusted by the phase comparator and the shift register so that the phase difference is made 0.
摘要翻译：内部时钟信号发生电路包括选择器，延迟线，2分频器，相位比较器和移位寄存器。选择器交替地选择从延迟线输出的外部时钟信号和内部时钟信号，并将选择的信号输出到延迟线。接收信号的延迟线延迟外部时钟信号，并延迟其自身输出的内部时钟信号。 2分频器将内部时钟信号的频率除以2.相位比较器比较外部时钟信号和2分频器的输出信号的相位。延迟线的延迟时间由相位比较器和移位寄存器调整，使得相位差为0。

56. 发明授权

US5940328A Synchronous semiconductor device with memory chips in a module for controlling output of strobe signal for trigger in reading data 失效
标题翻译：具有存储器芯片的同步半导体器件，用于控制用于在读取数据中触发的选通信号的输出
公开(公告)号：US5940328A
公开(公告)日：1999-08-17
申请号：US917211
申请日：1997-08-25
申请人： Hisashi Iwamoto , Wataru Sakamoto
发明人： Hisashi Iwamoto , Wataru Sakamoto
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C11/407 , G11C16/04
CPC分类号： G11C7/1072 , G11C7/22
摘要： One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1)) inputted to the adjacent first memory chip (MC(i-1)) as a data mask control signal (DQMCi), and stops outputting the strobe signal (QS) when both the data mask signal (DQMi) for the second memory chip (MCi) and the data mask control signal (DQMCi) are activated. Each memory chip (MCi) receives the data mask signal (DQMi) and stops outputting data. In a synchronous DRAM using a strobe signal as a trigger, this configuration allows reduction in the number of strobe signals.
摘要翻译：在每个模块中从一组两个相邻的存储器芯片（MC（i-1），MCi）输出一个选通信号（QS）。在每组中，第二存储器芯片（MCi）接收输入到相邻的第一存储器芯片（MC（i-1））的数据掩码信号（DQM（i-1））作为数据掩码控制信号（DQMCi），以及当第二存储器芯片（MCi）的数据掩码信号（DQMi）和数据掩码控制信号（DQMCi）都被激活时，停止输出选通信号（QS）。每个存储器芯片（MCi）接收数据屏蔽信号（DQMi）并停止输出数据。在使用选通信号作为触发的同步DRAM中，该配置允许减少选通信号的数量。

57. 发明授权

US5276651A Voltage generating device generating a voltage at a constant level and operating method thereof 失效
标题翻译：产生恒定电压的电压产生装置及其操作方法
公开(公告)号：US5276651A
公开(公告)日：1994-01-04
申请号：US953376
申请日：1992-09-30
申请人： Wataru Sakamoto
发明人： Wataru Sakamoto
IPC分类号： G11C11/407 , G05F3/24 , G11C5/14 , G11C11/408 , G11C16/06 , H02M3/07 , H03K19/096
CPC分类号： G11C5/146 , G05F3/24 , G11C5/145 , G11C5/147
摘要： A circuit of a structure in which one end of a serial connection circuit of two capacitors is grounded, and the potential of another end is switched in a constant cycle is disclosed as a voltage generating circuit applicable to a half Vcc generating circuit, a substrate bias circuit, or the like. Electrical connection between a connection point between the capacitors and a predetermined load and electrical connection between the connection point and ground are controlled so that the potential of the connection point attains to be a constant potential in accordance with the ratio between the capacitance of the two capacitors in response to switching of the potential of the "another end" to a predetermined potential. As a result, a half Vcc generating circuit with reduced power consumption and layout area and a substrate bias circuit capable of biasing a semiconductor substrate to an arbitrary potential are realized.
摘要翻译：公开了一种结构的电路，其中两个电容器的串联连接电路的一端接地，另一端的电位以恒定周期被切换，作为适用于半Vcc发生电路的电压发生电路，衬底偏置电路等。控制电容器与预定负载之间的连接点与连接点与接地之间的电连接之间的电气连接，使得连接点的电位根据两个电容器的电容之间的比例达到恒定电位响应于“另一端”的电位切换到预定电位。结果，实现了具有降低的功耗和布局面积的半Vcc生成电路和能够将半导体衬底偏置到任意电位的衬底偏置电路。

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