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51. 发明授权

US07355215B2 Field effect transistors (FETs) having multi-watt output power at millimeter-wave frequencies 有权
标题翻译：在毫米波频率下具有多瓦功率的场效应晶体管（FET）
公开(公告)号：US07355215B2
公开(公告)日：2008-04-08
申请号：US11005423
申请日：2004-12-06
申请人： Primit Parikh , Yifeng Wu , Adam William Saxler
发明人： Primit Parikh , Yifeng Wu , Adam William Saxler
IPC分类号： H01L29/739
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/2003 , H01L29/41725
摘要： High electron mobility transistors (HEMT) are provided having an output power of greater than 3.0 Watts when operated at a frequency of at least 30 GHz. The HEMT has a power added efficiency (PAE) of at least about 20 percent and/or a gain of at least about 7.5 dB. The total width of the HEMT is less than about 6.0 mm.
摘要翻译：提供高电子迁移率晶体管（HEMT），其在至少30GHz的频率下工作时具有大于3.0瓦特的输出功率。 HEMT具有至少约20％的功率附加效率（PAE）和/或至少约7.5dB的增益。 HEMT的总宽度小于约6.0mm。

52. 发明申请

US20070205433A1 Insulating gate AlGaN/GaN HEMTs 审中-公开
标题翻译：绝缘栅AlGaN / GaN HEMT
公开(公告)号：US20070205433A1
公开(公告)日：2007-09-06
申请号：US11799786
申请日：2007-05-03
申请人： Primit Parikh , Umesh Mishra , Yifeng Wu
发明人： Primit Parikh , Umesh Mishra , Yifeng Wu
IPC分类号： H01L21/338 , H01L29/06
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/432 , H01L29/517 , H01L29/518 , H01L29/7783 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.
摘要翻译：公开了具有薄AlGaN层的AlGaN / GaN HEMT以减少陷阱并且还具有附加层以减少栅极泄漏并增加最大驱动电流。根据本发明的一个HEMT包括其上具有阻挡半导体层的高电阻率半导体层。阻挡层具有比高电阻率层更宽的带隙，并且层之间形成2DEG。源极和漏极触点接触阻挡层，阻挡层的一部分表面被触点覆盖。绝缘层包括在阻挡层的未覆盖表面上，并且绝缘层上包括栅极接触。绝缘层对栅极漏电流形成屏障，也有助于增加HEMT的最大电流驱动。本发明还包括用于制造根据本发明的HEMT的方法。在一种方法中，HEMT及其绝缘层使用金属有机化学气相沉积（MOCVD）制造。在另一种方法中，在溅射室中将绝缘层溅射到HEMT的顶表面上。

53. 发明申请

US20070059873A1 Fabrication of single or multiple gate field plates 有权
标题翻译：制造单栅极或多栅极场板
公开(公告)号：US20070059873A1
公开(公告)日：2007-03-15
申请号：US10570964
申请日：2004-09-09
申请人： Alessandro Chini , Umesh Mishra , Primit Parikh , Yifeng Wu
发明人： Alessandro Chini , Umesh Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L21/8238
CPC分类号： H01L29/404 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/401 , H01L29/402 , H01L29/41766 , H01L29/42312 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/785
摘要： A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
摘要翻译：使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

54. 发明申请

US20050242366A1 Gallium nitride based diodes with low forward voltage and low reverse current operation 有权
标题翻译：具有低正向电压和低反向电流操作的氮化镓基二极管
公开(公告)号：US20050242366A1
公开(公告)日：2005-11-03
申请号：US11173035
申请日：2005-06-30
申请人： Primit Parikh , Umesh Mishra
发明人： Primit Parikh , Umesh Mishra
IPC分类号： H01L29/20 , H01L29/22 , H01L29/47 , H01L29/872 , H01L29/88
CPC分类号： H01L29/475 , H01L29/2003 , H01L29/872 , H01L29/88
摘要： New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
摘要翻译：公开了具有低导通状态电压（V SUB）的新的基于III族的二极管，并且保持反向电流（I SUB）的结构相对较低。本发明的一个实施例是由GaN材料系统制成的肖特基势垒二极管，其中费米能级（或表面电位）不被固定。金属 - 半导体结的势垒电位根据所使用的金属的种类而变化，并且使用特定的金属降低了二极管的肖特基势垒电位，并导致在0.1-0.3V的范围内的V < 。在另一个实施例中，在肖特基二极管半导体材料上形成沟槽结构以减少反向漏电流。并且包括多个平行的等间距的沟槽，其间具有相邻沟槽之间的台面区域。本发明的第三实施例提供了由电子穿过势垒电位而不是在其上的隧穿形成的具有低V bias的GaN隧道二极管。该实施例还可以具有沟槽结构以减少反向漏电流。

55. 发明申请

US20050051796A1 Wide bandgap transistor devices with field plates 有权
标题翻译：具有现场板的宽带隙晶体管器件
公开(公告)号：US20050051796A1
公开(公告)日：2005-03-10
申请号：US10930160
申请日：2004-08-31
申请人： Primit Parikh , Yifeng Wu
发明人： Primit Parikh , Yifeng Wu
IPC分类号： H01L29/06 , H01L29/20 , H01L29/40 , H01L29/423 , H01L29/778 , H01L29/812 , H01L31/0328
CPC分类号： H01L29/402 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/7787 , H01L29/812
摘要： A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact.
摘要翻译：一种晶体管结构，包括具有金属源的有源半导体层和与该有源层电接触形成的漏极触点。在源极和漏极接触之间形成栅极接触，用于调制有源层内的电场。在有源层上方形成间隔层，形成在间隔层上方的导电场板，从栅极接触边缘向漏极接触延伸一段距离Lf。场板电连接到门接触。

56. 发明申请

US20050006669A1 Group III nitride based flip-chip integrated circuit and method for fabricating 有权
标题翻译： III族氮化物倒装芯片集成电路及其制造方法
公开(公告)号：US20050006669A1
公开(公告)日：2005-01-13
申请号：US10916819
申请日：2004-08-11
申请人： Umesh Mishra , Primit Parikh , Yifeng Wu
发明人： Umesh Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L21/8252 , H01L23/14 , H01L23/367 , H01L23/66 , H01L27/06 , H01L29/20 , H01L29/778 , H01L27/10
CPC分类号： H05K1/0206 , H01L21/8252 , H01L23/147 , H01L23/367 , H01L23/3677 , H01L23/66 , H01L27/0605 , H01L29/2003 , H01L29/7787 , H01L2224/16235 , H01L2224/16238 , H01L2224/1703 , H01L2224/73253 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/10329 , H01L2924/12032 , H01L2924/14 , H01L2924/1423 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19105 , H01L2924/30105 , H05K1/181 , H05K2201/066 , Y10T29/4913 , H01L2924/0002 , H01L2924/00
摘要： A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals. The present invention is particularly applicable to Group III nitride based active semiconductor devices grown on SiC substrates. The passive components and interconnects can then be formed on a lower cost, higher diameter wafer made of GaAs or Si. After separation, the Group III devices can be flip-chip mounted on the GaAs or Si substrate.
摘要翻译：公开了一种用于制造集成电路的倒装芯片集成电路和方法。根据本发明的方法包括在晶片上形成多个有源半导体器件并分离有源半导体器件。无源元件和互连形成在电路基板的表面上，并且通过电路基板形成至少一个导电通孔。至少一个有源半导体器件被倒装芯片安装在电路基板上，其中至少一个接合焊盘与导电通孔之一电接触。根据本发明的倒装芯片集成电路包括在一个表面上具有无源部件和互连的电路基板，并且可以具有通过其的导电通孔。有源半导体器件被倒装安装在电路基板上，所述至少一个通孔中的一个与该器件的至少一个端子中的一个接触。本发明特别适用于在SiC衬底上生长的III族氮化物基有源半导体器件。然后可以在GaAs或Si制成的较低成本，更高直径的晶圆上形成无源部件和互连。分离后，III组器件可以倒装安装在GaAs或Si衬底上。

57. 发明授权

US09773877B2 Wide bandgap field effect transistors with source connected field plates 有权
公开(公告)号：US09773877B2
公开(公告)日：2017-09-26
申请号：US10958945
申请日：2004-10-04
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
IPC分类号： H01L31/0328 , H01L29/40 , H01L29/417 , H01L29/812 , H01L29/20
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/41725 , H01L29/42316 , H01L29/812
摘要： A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the MESFET.

58. 发明授权

US09041064B2 High voltage GaN transistor 有权
标题翻译：高压GaN晶体管
公开(公告)号：US09041064B2
公开(公告)日：2015-05-26
申请号：US13445632
申请日：2012-04-12
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, drain, and gate. A first spacer layer is between the source and the gate and a second spacer layer between the drain and the gate. A first field plate on the first spacer layer and a second field plate on the second spacer layer are connected to the gate. A third field plate connected to the source is on a third spacer layer, which is on the gate and the first and second field plates and spacer layers. The transistor exhibits a blocking voltage of at least 600 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 5.0 or 5.3 mΩ-cm2, respectively, and at least 900 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 6.6 or 7.0 mΩ-cm2, respectively.
摘要翻译：多场板晶体管包括具有源极，漏极和栅极的有源区域。源极和栅极之间的第一间隔层和漏极与栅极之间的第二间隔层。第一间隔层上的第一场板和第二间隔层上的第二场板连接到栅极。连接到源极的第三场板位于第三间隔层上，第三间隔层位于栅极上，第一和第二场板和间隔层。晶体管显示至少600伏特的阻断电压，同时支持至少2或3安培的电流，分别具有不超过5.0或5.3mΩ/ cm 2的导通电阻和至少900V的电流，同时支持至少2的电流或3安培，导通电阻分别不超过6.6或7.0 m＆OHgr; -cm2。

59. 发明授权

US08664695B2 Wide bandgap transistors with multiple field plates 有权
标题翻译：具有多个场板的宽带隙晶体管
公开(公告)号：US08664695B2
公开(公告)日：2014-03-04
申请号：US12497468
申请日：2009-07-02
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
IPC分类号： H01L29/778
CPC分类号： H01L29/404 , H01L29/2003 , H01L29/7787
摘要： A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor layers, each of which extends from the edge of the gate toward the drain electrode, and each of which is isolated from said semiconductor layers and from the others of the field plates. The topmost of the field plates is electrically connected to the source electrode and the others of the field plates are electrically connected to the gate or the source electrode.
摘要翻译：一种晶体管，包括在衬底上的多个有源半导体层，源极和漏极与半导体层接触。在源极和漏极之间以及多个半导体层上形成栅极。多个场板布置在半导体层之上，每个场板从栅极的边缘延伸到漏电极，并且每个场板与所述半导体层和场板中的其它层隔离。场板的最顶端电连接到源电极，而另外的场板电连接到栅极或源电极。

60. 发明授权

US08541818B2 Semiconductor heterostructure diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US08541818B2
公开(公告)日：2013-09-24
申请号：US13533339
申请日：2012-06-26
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Ilan Ben-Yaacov
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Ilan Ben-Yaacov
IPC分类号： H01L33/00 , H01L29/739
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2 DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2 DEG, forming an ohmic contact with the layer containing the 2 DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2°的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触器连接到2°，与含有2°的层形成欧姆接触。

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