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51. 发明授权

US06490708B2 Method of integrated circuit design by selection of noise tolerant gates 失效
公开(公告)号：US06490708B2
公开(公告)日：2002-12-03
申请号：US09812211
申请日：2001-03-19
申请人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
发明人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
IPC分类号： G06E1750
CPC分类号： G06F17/505
摘要： A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

52. 发明授权

US06473881B1 Pattern-matching for transistor level netlists 失效
标题翻译：晶体管级网表的模式匹配
公开(公告)号：US06473881B1
公开(公告)日：2002-10-29
申请号：US09702313
申请日：2000-10-31
申请人： Valerie D. Lehner , John M. Cohn , Ulrich A. Finkler
发明人： Valerie D. Lehner , John M. Cohn , Ulrich A. Finkler
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers. It further provides rooted sub-graph isomorphism so that a user can query whether a particular pattern is embedded at a particular location in the main circuit design, utilizing inexact sub-graph isomorphism
摘要翻译：单一模式匹配算法，允许精确和不精确的模式匹配，以便晶体管级设计自动化工具可以在制造之前可靠地执行时序分析，电气规则检查，噪声分析，测试模式生成，正式设计验证等定制逻辑。用户（电路设计者）指定每个模式外部网络中的哪一个可以精确匹配（附加到Vdd，连接到GND，并与其他外部网络短接），其余模式外部网络连接使用精确同构约束。本文描述的方法实现了电路设计者必须生成的图案数量的显着减少，并且通过向电路设计者提供不精确的图案匹配器，完全不需要指数数目的图案。它还提供了根系的子图同构，使得用户可以在主电路设计中的特定位置查询特定模式是否被嵌入，利用不精确的子图同构

53. 发明授权

US09332362B2 Acoustic diagnosis and correction system 有权
公开(公告)号：US09332362B2
公开(公告)日：2016-05-03
申请号：US13613926
申请日：2012-09-13
申请人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
发明人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
IPC分类号： H04R29/00
CPC分类号： H04R29/00 , G07C5/008 , G07C5/0808
摘要： An acoustic monitoring system includes a portable acoustic detection device, a sound analysis device and a confidence level device. The portable acoustic detection device is capable of receiving sound at one or more locations near a sound-producing device. The sound analysis device receives the sound from the portable sound detection device, determines a diagnosis based on a comparison between the sound and pre-recorded sound data, and outputs the diagnosis to the portable acoustic detection device. The sound analysis device also determines a corrective action for inhibiting the sound, which is also output to the portable sound detection device. The confidence level device determines a confidence level of the diagnosis indicating a likelihood that the diagnosis is successfully diagnosed.

54. 发明申请

US20140074435A1 ACOUSTIC DIAGNOSIS AND CORRECTION SYSTEM 审中-公开
公开(公告)号：US20140074435A1
公开(公告)日：2014-03-13
申请号：US13613926
申请日：2012-09-13
申请人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
发明人： John M. Cohn , James R. Kozloski , Clifford A. Pickover , Jinjun Xiong
IPC分类号： G01N29/14 , G06F15/00
CPC分类号： H04R29/00 , G07C5/008 , G07C5/0808
摘要： An acoustic monitoring system includes a portable acoustic detection device, a sound analysis device and a confidence level device. The portable acoustic detection device is capable of receiving sound at one or more locations near a sound-producing device. The sound analysis device receives the sound from the portable sound detection device, determines a diagnosis based on a comparison between the sound and pre-recorded sound data, and outputs the diagnosis to the portable acoustic detection device. The sound analysis device also determines a corrective action for inhibiting the sound, which is also output to the portable sound detection device. The confidence level device determines a confidence level of the diagnosis indicating a likelihood that the diagnosis is successfully diagnosed.

55. 发明授权

US08565510B2 Methods for reading a feature pattern from a packaged die 失效
标题翻译：从封装模具读取特征图案的方法
公开(公告)号：US08565510B2
公开(公告)日：2013-10-22
申请号：US13359818
申请日：2012-01-27
申请人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
发明人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
IPC分类号： G06K9/00
CPC分类号： H01L23/544 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/78 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
摘要翻译：用于跟踪从晶片分离后的裸片的身份的方法。产品芯片和管芯包括形成在后端（BEOL）布线结构的金属化水平中的特征图案。图案中的特征包含与管芯相关的信息，例如包括用于制造管芯的晶片识别的唯一标识符和晶片上的管芯的产品芯片位置。这些特征可以通过穿透到包装的模具中的电磁辐射束的帮助来成像，并且以促进成像的方式由特征的存在而改变。

56. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

57. 发明授权

US08187897B2 Fabricating product chips and die with a feature pattern that contains information relating to the product chip 有权
标题翻译：使用包含与产品芯片有关的信息的特征图案来制造产品芯片和芯片
公开(公告)号：US08187897B2
公开(公告)日：2012-05-29
申请号：US12193825
申请日：2008-08-19
申请人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
发明人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/78 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
摘要翻译：产品芯片和芯片，用于制造产品芯片的方法以及用于跟踪从晶片分离后的芯片的身份的方法。产品芯片和管芯包括形成在后端（BEOL）布线结构的金属化水平中的特征图案。图案中的特征包含与管芯相关的信息，诸如唯一的标识符，其包括用于制造管芯的晶片的晶片识别和晶片上的管芯的产品芯片位置。这些特征可以通过穿透到包装的模具中的电磁辐射束的帮助来成像，并且以促进成像的方式由特征的存在而改变。

58. 发明申请

US20100044858A1 Product Chips and Die With a Feature Pattern That Contains Information Relating to the Product Chip, Methods for Fabricating Such Product Chips and Die, and Methods for Reading a Feature Pattern From a Packaged Die 有权
标题翻译：具有包含与产品芯片有关的信息的特征图案的产品芯片和模具，用于制造这种产品芯片和芯片的方法以及从封装模具读取特征图案的方法
公开(公告)号：US20100044858A1
公开(公告)日：2010-02-25
申请号：US12193825
申请日：2008-08-19
申请人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
发明人： John M. Cohn , Mark J. Flemming , John C. Malinowski , Karl V. Swanke
IPC分类号： H01L23/544 , H01L21/768 , H01L21/50 , H01L21/66
CPC分类号： H01L23/544 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/78 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
摘要翻译：产品芯片和芯片，用于制造产品芯片的方法以及用于跟踪从晶片分离后的芯片的身份的方法。产品芯片和管芯包括形成在后端（BEOL）布线结构的金属化水平中的特征图案。图案中的特征包含与管芯相关的信息，诸如唯一的标识符，其包括用于制造管芯的晶片的晶片识别和晶片上的管芯的产品芯片位置。这些特征可以通过穿透到包装的模具中的电磁辐射束的帮助来成像，并且以促进成像的方式由特征的存在而改变。

59. 发明申请

US20100023913A1 METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING 有权
标题翻译： IC接线优化方法，包括在路由和之后的线路宽带化
公开(公告)号：US20100023913A1
公开(公告)日：2010-01-28
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

60. 发明申请

US20090259983A1 METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING 有权
标题翻译：设计产品芯片的设计方法，设计分析，特征分析和理论学习
公开(公告)号：US20090259983A1
公开(公告)日：2009-10-15
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

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